Abstract
Embedded memories occupy an increasingly dominant part of the area and power budgets of modern SoCs. Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for two-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel 4-transistor gain-cell, which provides up-to two independent read and write ports (2R2W), with a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability. An 8 kbit memory macro was implemented in a 28 nm FD-SOI technology, offering up-to 3 × reduction in bitcell area compared to other dual-ported SRAM memory options, and 100% memory availability, as opposed to conventional dynamic memories.
Original language | English |
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Title of host publication | 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 589-592 |
Number of pages | 4 |
ISBN (Electronic) | 9781538695623 |
DOIs | |
State | Published - 2 Jul 2018 |
Event | 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 - Bordeaux, France Duration: 9 Dec 2018 → 12 Dec 2018 |
Publication series
Name | 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 |
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Conference
Conference | 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 |
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Country/Territory | France |
City | Bordeaux |
Period | 9/12/18 → 12/12/18 |
Bibliographical note
Publisher Copyright:© 2018 IEEE.
Keywords
- 1R1W
- 2R2W
- GC-eDRAM
- configurable memory
- dual-port
- refresh
- two-port