Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism

Roman Golman; Robert Giterman; Adam Teman

doi:10.1109/ICECS.2018.8617861

Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism

Roman Golman, Robert Giterman, Adam Teman

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern SoCs. Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for two-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel 4-transistor gain-cell, which provides up-to two independent read and write ports (2R2W), with a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability. An 8 kbit memory macro was implemented in a 28 nm FD-SOI technology, offering up-to 3 × reduction in bitcell area compared to other dual-ported SRAM memory options, and 100% memory availability, as opposed to conventional dynamic memories.

Original language	English
Title of host publication	2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	589-592
Number of pages	4
ISBN (Electronic)	9781538695623
DOIs	https://doi.org/10.1109/ICECS.2018.8617861
State	Published - 17 Jan 2019
Event	25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 - Bordeaux, France Duration: 9 Dec 2018 → 12 Dec 2018

Publication series

Name	2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

Conference

Conference	25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Country/Territory	France
City	Bordeaux
Period	9/12/18 → 12/12/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

1R1W
2R2W
GC-eDRAM
configurable memory
dual-port
refresh
two-port

Access to Document

10.1109/ICECS.2018.8617861

Cite this

Golman, R., Giterman, R., & Teman, A. (2019). Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. In 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 (pp. 589-592). [8617861] (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2018.8617861

Golman, Roman ; Giterman, Robert ; Teman, Adam. / Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 589-592 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

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abstract = "Embedded memories occupy an increasingly dominant part of the area and power budgets of modern SoCs. Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for two-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel 4-transistor gain-cell, which provides up-to two independent read and write ports (2R2W), with a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability. An 8 kbit memory macro was implemented in a 28 nm FD-SOI technology, offering up-to 3 × reduction in bitcell area compared to other dual-ported SRAM memory options, and 100% memory availability, as opposed to conventional dynamic memories.",

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Golman, R, Giterman, R & Teman, A 2019, Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. in 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018., 8617861, 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, Institute of Electrical and Electronics Engineers Inc., pp. 589-592, 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, Bordeaux, France, 9/12/18. https://doi.org/10.1109/ICECS.2018.8617861

Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. / Golman, Roman; Giterman, Robert; Teman, Adam.
2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 589-592 8617861 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Golman R, Giterman R, Teman A. Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. In 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 589-592. 8617861. (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018). doi: 10.1109/ICECS.2018.8617861

Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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