Abstract
The paper deals with the problem of decomposition of logic functions and their implementation in a form of
Multi Terminal Binary Decision Diagrams (MTBDD). The new logic decomposition method and the
implementation style, called concurrent decomposition, introduced in the paper leads to a compact VLSI
layout of locally interconnected logic elements. It is easily amenable to VLSI implementations of custom
design in deep submicron technology, where control over interconnect wiring and its delay becomes of
primary importance.
The proposed decomposition method is based on the algebra of D -polynomials reviewed in the paper. The
resulting decomposition is directly mapable onto special type of binary graph called Concurrent Multi
Terminal BDD. The paper describes both the theoretical fundamentals of the decomposition algorithm and its
certain implementation. Benchmark results are presented and analyzed. Guidelines for effective using of the
proposed technique are provided.
Original language | American English |
---|---|
Title of host publication | 7th International Workshop on Boolean Problems |
State | Published - 2006 |