CMOS based gates for blurring power information

Power analysis attacks have become one of the most significant security threats to modern cryptographic digital systems. In this paper, we introduce a new CMOS-based blurring gate (BG) which increases the immunity of a cryptographic system to these attacks. The BG switches randomly between two operational-modes, static and dynamic. When embedded in the crypto-core, the BGs enforce different and unpredictable arrival times (propagation delays) along the logic paths from inputs to outputs. This results in blurred power profiles and random propagation delays, which in turn mitigate power attacks. Simulation results and security analyses using system with embedded BG units with standard 65-nm technology, clearly show higher immunity to power analysis attacks over other standard-library based randomization technologies. The signal-to-noise ratio (SNR) decreases rapidly below 1 for a relatively small amount of BGs even with a large number of power traces in the worst case test environment.