Abstract
A new clockfeedthrough compensation scheme for switched- current systems is proposed. The circuit cancels both the signal dependent and the constant clockfeedthrough term. It is shown that this concept can be used to derive various sample-and-hold circuits, depending on the desired clock frequency, accuracy, and power dissipation.
| Original language | English |
|---|---|
| Pages (from-to) | 229-231 |
| Number of pages | 3 |
| Journal | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing |
| Volume | 42 |
| Issue number | 3 |
| DOIs | |
| State | Published - Mar 1995 |
| Externally published | Yes |
Bibliographical note
Funding Information:Manuscript received August 3, 1994; revised October 8, 1994. This work was supported by the KWF Jessi-Project, 2302.1 Eureka EU 127. This paper was recommended by Associate Editor S. Kiaei. The authors are with the Institute of Signal and Information Processing, Swiss Federal Institute of Technology, CH-8092 Zurich, Switzerland. IEEE Log Number 9407423.
Funding
Manuscript received August 3, 1994; revised October 8, 1994. This work was supported by the KWF Jessi-Project, 2302.1 Eureka EU 127. This paper was recommended by Associate Editor S. Kiaei. The authors are with the Institute of Signal and Information Processing, Swiss Federal Institute of Technology, CH-8092 Zurich, Switzerland. IEEE Log Number 9407423.
| Funders | Funder number |
|---|---|
| Kommission zur Förderung der wissenschaftlichen Forschung | 2302.1 Eureka EU 127 |