Abstract
Dynamic logic has become a niche approach in circuit design, mainly due to the reliability limitations that have been aggravated with process down-scaling. To that extent, the performance and area benefits of dynamic design approaches, such as the integration of the Clocked CMOS (C2MOS) approach, are left on the table. In this article, we propose employing the Three-Independent-Gate Field-Effect Transistor (TIGFET) technology for the implementation of the C2MOS approach, which we call the Clocked Complementary TIG (C2TIG) approach. Electrical simulations at 22nm demonstrate the enhanced robustness of the C2TIG approach, while providing gains in power, performance, and area. Finally, new design opportunities for synchronous systems are demonstrated with the C2TIG approach.
| Original language | English |
|---|---|
| Article number | 8959396 |
| Pages (from-to) | 123-136 |
| Number of pages | 14 |
| Journal | IEEE Transactions on Nanotechnology |
| Volume | 19 |
| DOIs | |
| State | Published - 2020 |
Bibliographical note
Publisher Copyright:© 2002-2012 IEEE.
Funding
Manuscript received November 4, 2019; accepted January 4, 2020. Date of publication January 14, 2020; date of current version January 20, 2020. This work was kindly supported by the Israel Science Fund under grant number 996/18. The review of this article was arranged by Associate Editor Dr. M. Niemier. (Corresponding author: Daniel Vana.) D. Vana is with the School of Electrical Engineering, Tel-Aviv University, Tel Aviv-Yafo 69978, Israel (e-mail: [email protected]).
| Funders | Funder number |
|---|---|
| israel science fund | 996/18 |
Keywords
- Field effect transistors
- integrated circuit reliability
- integrated circuit technology
- nanoscale devices
- sequential circuits