Dynamic logic has become a niche approach in circuit design, mainly due to the reliability limitations that have been aggravated with process down-scaling. To that extent, the performance and area benefits of dynamic design approaches, such as the integration of the Clocked CMOS (C2MOS) approach, are left on the table. In this article, we propose employing the Three-Independent-Gate Field-Effect Transistor (TIGFET) technology for the implementation of the C2MOS approach, which we call the Clocked Complementary TIG (C2TIG) approach. Electrical simulations at 22nm demonstrate the enhanced robustness of the C2TIG approach, while providing gains in power, performance, and area. Finally, new design opportunities for synchronous systems are demonstrated with the C2TIG approach.
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© 2002-2012 IEEE.
- Field effect transistors
- integrated circuit reliability
- integrated circuit technology
- nanoscale devices
- sequential circuits