Cascade scheme for concurrent errors detection

Ilya Levin; Vladimir Ostrovsky; Osnat Keren; Vladimir Sinelnikov

doi:10.1109/DSD.2006.31

Cascade scheme for concurrent errors detection

Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladimir Sinelnikov

Tel Aviv University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades followed by parity checking their output logic. The algorithm for partitioning the scheme into cascades is provided. An universal scheme of Finite State Machine (FSM) with the cascade errors detection is presented and investigated. The scheme does not require any redundant coding variables. Benchmark results are presented and show significantly low overhead requirement.

Original language	English
Title of host publication	Proceedings of the 9th EUROMICRO Conference on Digital System Design
Subtitle of host publication	Architectures, Methods and Tools, DSD 2006
Pages	359-365
Number of pages	7
DOIs	https://doi.org/10.1109/DSD.2006.31
State	Published - 2006
Event	9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006 - Dubrovnik, Croatia Duration: 30 Aug 2006 → 1 Sep 2006

Publication series

Name	Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

Conference

Conference	9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006
Country/Territory	Croatia
City	Dubrovnik
Period	30/08/06 → 1/09/06

Access to Document

10.1109/DSD.2006.31

Cite this

Levin, I., Ostrovsky, V., Keren, O., & Sinelnikov, V. (2006). Cascade scheme for concurrent errors detection. In Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006 (pp. 359-365). Article 1690062 (Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006). https://doi.org/10.1109/DSD.2006.31

@inproceedings{b7cb71b4fbbd4c319e929dddd2f71be5,

title = "Cascade scheme for concurrent errors detection",

abstract = "The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades followed by parity checking their output logic. The algorithm for partitioning the scheme into cascades is provided. An universal scheme of Finite State Machine (FSM) with the cascade errors detection is presented and investigated. The scheme does not require any redundant coding variables. Benchmark results are presented and show significantly low overhead requirement.",

author = "Ilya Levin and Vladimir Ostrovsky and Osnat Keren and Vladimir Sinelnikov",

year = "2006",

doi = "10.1109/DSD.2006.31",

language = "אנגלית",

isbn = "0769526098",

series = "Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006",

pages = "359--365",

booktitle = "Proceedings of the 9th EUROMICRO Conference on Digital System Design",

note = "9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006 ; Conference date: 30-08-2006 Through 01-09-2006",

}

Levin, I, Ostrovsky, V, Keren, O & Sinelnikov, V 2006, Cascade scheme for concurrent errors detection. in Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006., 1690062, Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006, pp. 359-365, 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006, Dubrovnik, Croatia, 30/08/06. https://doi.org/10.1109/DSD.2006.31

Cascade scheme for concurrent errors detection. / Levin, Ilya; Ostrovsky, Vladimir; Keren, Osnat et al.
Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006. 2006. p. 359-365 1690062 (Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Cascade scheme for concurrent errors detection

AU - Levin, Ilya

AU - Ostrovsky, Vladimir

AU - Keren, Osnat

AU - Sinelnikov, Vladimir

PY - 2006

Y1 - 2006

N2 - The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades followed by parity checking their output logic. The algorithm for partitioning the scheme into cascades is provided. An universal scheme of Finite State Machine (FSM) with the cascade errors detection is presented and investigated. The scheme does not require any redundant coding variables. Benchmark results are presented and show significantly low overhead requirement.

AB - The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades followed by parity checking their output logic. The algorithm for partitioning the scheme into cascades is provided. An universal scheme of Finite State Machine (FSM) with the cascade errors detection is presented and investigated. The scheme does not require any redundant coding variables. Benchmark results are presented and show significantly low overhead requirement.

UR - http://www.scopus.com/inward/record.url?scp=34547978479&partnerID=8YFLogxK

U2 - 10.1109/DSD.2006.31

DO - 10.1109/DSD.2006.31

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:34547978479

SN - 0769526098

SN - 9780769526096

T3 - Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

SP - 359

EP - 365

BT - Proceedings of the 9th EUROMICRO Conference on Digital System Design

T2 - 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006

Y2 - 30 August 2006 through 1 September 2006

ER -

Levin I, Ostrovsky V, Keren O, Sinelnikov V. Cascade scheme for concurrent errors detection. In Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006. 2006. p. 359-365. 1690062. (Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006). doi: 10.1109/DSD.2006.31

Cascade scheme for concurrent errors detection

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this