Abstract
Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing the CMP cache hierarchy and optimally allocating area among hierarchy levels under such constrained resources is developed. The optimization framework is extended by incorporating the impact of data sharing on cache miss rate. An analytical model for cache access time as a function of cache size is proposed and verified using CACTI simulation.
Original language | English |
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Article number | 6560077 |
Pages (from-to) | 69-72 |
Number of pages | 4 |
Journal | IEEE Computer Architecture Letters |
Volume | 13 |
Issue number | 2 |
DOIs | |
State | Published - 1 Jul 2014 |
Externally published | Yes |
Bibliographical note
Publisher Copyright:© 2002-2011 IEEE.
Keywords
- Analytical Performance Models
- Cache Hierarchy
- Chip Multiprocessor
- Resource Allocation Optimization