Cache Hierarchy Optimization

Leonid Yavits, Amir Morad, Ran Ginosar

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing the CMP cache hierarchy and optimally allocating area among hierarchy levels under such constrained resources is developed. The optimization framework is extended by incorporating the impact of data sharing on cache miss rate. An analytical model for cache access time as a function of cache size is proposed and verified using CACTI simulation.

Original languageEnglish
Article number6560077
Pages (from-to)69-72
Number of pages4
JournalIEEE Computer Architecture Letters
Issue number2
StatePublished - 1 Jul 2014
Externally publishedYes

Bibliographical note

Publisher Copyright:
© 2002-2011 IEEE.


  • Analytical Performance Models
  • Cache Hierarchy
  • Chip Multiprocessor
  • Resource Allocation Optimization


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