Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology

Pascal Meinerzhagen; S. M.Yasser Sherazi; Andreas Burg; Joachim Neves Rodrigues

doi:10.1109/JETCAS.2011.2162159

Benchmarking of standard-cell based memories in the sub-V_T domain in 65-nm CMOS technology

Pascal Meinerzhagen, S. M.Yasser Sherazi, Andreas Burg, Joachim Neves Rodrigues

Research output: Contribution to journal › Article › peer-review

59 Scopus citations

Abstract

In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-V_T SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-V_T domain of various SCM architectures are evaluated by means of a gate-level sub-V_T characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-V_T SRAM designs.

Original language	English
Article number	5976987
Pages (from-to)	173-182
Number of pages	10
Journal	IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Volume	1
Issue number	2
DOIs	https://doi.org/10.1109/JETCAS.2011.2162159
State	Published - Jun 2011
Externally published	Yes

Bibliographical note

Funding Information:
Manuscript received December 31, 2010; revised May 23, 2011; accepted June 21, 2011. Date of publication August 08, 2011; date of current version August 19, 2011. This work was kindly supported by the Swiss National Science Foundation under the project number PP002-119057. The project was conducted at Lund University with financial support from the Swedish VINNOVA Industrial Excellence Centre (SOS) and Swedish Foundation for Strategic Research (SSF). This paper was recommended by Guest Editor E. Macii.

Funding

Manuscript received December 31, 2010; revised May 23, 2011; accepted June 21, 2011. Date of publication August 08, 2011; date of current version August 19, 2011. This work was kindly supported by the Swiss National Science Foundation under the project number PP002-119057. The project was conducted at Lund University with financial support from the Swedish VINNOVA Industrial Excellence Centre (SOS) and Swedish Foundation for Strategic Research (SSF). This paper was recommended by Guest Editor E. Macii.

Funders	Funder number
Swedish VINNOVA
Schweizerischer Nationalfonds zur Förderung der Wissenschaftlichen Forschung	PP002-119057
Stiftelsen för Strategisk Forskning

Keywords

Embedded memory
flip-flop array
latch array
low-power
process parameter variations
reliability
sub-V operation

Access to Document

10.1109/JETCAS.2011.2162159

Cite this

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abstract = "In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-VT SRAM designs.",

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