In this paper, standard-cell based memories (SCMs) are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-VT SRAM designs.
|Number of pages||10|
|Journal||IEEE Journal on Emerging and Selected Topics in Circuits and Systems|
|State||Published - Jun 2011|
Bibliographical noteFunding Information:
Manuscript received December 31, 2010; revised May 23, 2011; accepted June 21, 2011. Date of publication August 08, 2011; date of current version August 19, 2011. This work was kindly supported by the Swiss National Science Foundation under the project number PP002-119057. The project was conducted at Lund University with financial support from the Swedish VINNOVA Industrial Excellence Centre (SOS) and Swedish Foundation for Strategic Research (SSF). This paper was recommended by Guest Editor E. Macii.
- Embedded memory
- flip-flop array
- latch array
- process parameter variations
- sub-V operation