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Balanced block spacing for VLSI layout
Israel Cederbaum
, Israel Koren
,
Shmuel Wimer
Technion-Israel Institute of Technology
University of Massachusetts
IBM
Research output
:
Contribution to journal
›
Article
›
peer-review
4
Scopus citations
Overview
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Keyphrases
VLSI Layout
100%
Block Spaces
100%
Balance Problem
66%
Iterative Algorithm
33%
Solution Uniqueness
33%
Graph Model
33%
Chip Area
33%
Solution Existence
33%
One-dimensional Space
33%
Placement Algorithm
33%
Uniform Space
33%
Two-dimensional Problems
33%
Adjacency Relation
33%
Engineering
Building Block
100%
Adjacent Block
100%
One Dimensional
50%
Two Dimensional
50%
Iterative Algorithm
50%
Chip Area
50%
Dimensional Space
50%
Dimensional Problem
50%
Computer Science
Building-Blocks
100%
Adjacent Block
100%
Iterative Algorithm
50%
Routing Requirement
50%
Adjacency Relation
50%
Placement Algorithm
50%
Dimensional Space
50%
Dimensional Problem
50%
Mathematics
Building Block
100%
Adjacency
50%
Graph Model
50%
Dimensional Space
50%
Dimensional Problem
50%