Automating Design for Yield: Silicon Learning to Predictive Models and Design Optimization

Srikanth Venkat Raman; Pongpachara Limpisathian; Pascal Meinerzhagen; Suriyaprakash Natarajan; Eric Yang

doi:10.1109/itc44778.2020.9325263

Automating Design for Yield: Silicon Learning to Predictive Models and Design Optimization

Srikanth Venkat Raman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang

Intel

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

We propose a framework to co-optimize Yield along with Power, Performance and Area (PPA) through the design flow from logic synthesis through placement and routing (APR). We accomplish this by learning from silicon using a combination of test/diagnosis, inline/metrology and Failure Analysis (FA) results to create predictive models using Machine Learning (ML) techniques that are then used during design. Simulation results across three different CPU and Graphics cores show promising results with projected yield improvements of 11-17% with no area and performance / timing penalty with respect to design targets but with tradeoffs to both static and dynamic power. Better joint exploration of the PPA space along with yield indicates it is possible to recover yield with close to iso-PPA with respect to design targets. Pre-silicon results show \sim 10.4% yield increase with iso-Area and-iso-performance and \sim 1% power penalty on a processor core.

Original language	English
Title of host publication	2020 IEEE International Test Conference, ITC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728191133
DOIs	https://doi.org/10.1109/itc44778.2020.9325263
State	Published - 1 Nov 2020
Externally published	Yes
Event	2020 IEEE International Test Conference, ITC 2020 - Washington, United States Duration: 1 Nov 2020 → 6 Nov 2020

Publication series

Name	Proceedings - International Test Conference
Volume	2020-November
ISSN (Print)	1089-3539

Conference

Conference	2020 IEEE International Test Conference, ITC 2020
Country/Territory	United States
City	Washington
Period	1/11/20 → 6/11/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE.

Keywords

APR
Defect Avoidance
Design Optimization
Design-for-Manufacturability (DFM)
Design-for-Yield (DFY)
Diagnosis
Logic Synthesis
PPA
Yield Improvement

Access to Document

10.1109/itc44778.2020.9325263

Cite this

Raman, S. V., Limpisathian, P., Meinerzhagen, P., Natarajan, S., & Yang, E. (2020). Automating Design for Yield: Silicon Learning to Predictive Models and Design Optimization. In 2020 IEEE International Test Conference, ITC 2020 Article 9325263 (Proceedings - International Test Conference; Vol. 2020-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/itc44778.2020.9325263

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title = "Automating Design for Yield: Silicon Learning to Predictive Models and Design Optimization",

abstract = "We propose a framework to co-optimize Yield along with Power, Performance and Area (PPA) through the design flow from logic synthesis through placement and routing (APR). We accomplish this by learning from silicon using a combination of test/diagnosis, inline/metrology and Failure Analysis (FA) results to create predictive models using Machine Learning (ML) techniques that are then used during design. Simulation results across three different CPU and Graphics cores show promising results with projected yield improvements of 11-17% with no area and performance / timing penalty with respect to design targets but with tradeoffs to both static and dynamic power. Better joint exploration of the PPA space along with yield indicates it is possible to recover yield with close to iso-PPA with respect to design targets. Pre-silicon results show \sim 10.4% yield increase with iso-Area and-iso-performance and \sim 1% power penalty on a processor core.",

keywords = "APR, Defect Avoidance, Design Optimization, Design-for-Manufacturability (DFM), Design-for-Yield (DFY), Diagnosis, Logic Synthesis, PPA, Yield Improvement",

author = "Raman, {Srikanth Venkat} and Pongpachara Limpisathian and Pascal Meinerzhagen and Suriyaprakash Natarajan and Eric Yang",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE International Test Conference, ITC 2020 ; Conference date: 01-11-2020 Through 06-11-2020",

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doi = "10.1109/itc44778.2020.9325263",

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Raman, SV, Limpisathian, P, Meinerzhagen, P, Natarajan, S & Yang, E 2020, Automating Design for Yield: Silicon Learning to Predictive Models and Design Optimization. in 2020 IEEE International Test Conference, ITC 2020., 9325263, Proceedings - International Test Conference, vol. 2020-November, Institute of Electrical and Electronics Engineers Inc., 2020 IEEE International Test Conference, ITC 2020, Washington, United States, 1/11/20. https://doi.org/10.1109/itc44778.2020.9325263

Automating Design for Yield: Silicon Learning to Predictive Models and Design Optimization. / Raman, Srikanth Venkat; Limpisathian, Pongpachara; Meinerzhagen, Pascal et al.
2020 IEEE International Test Conference, ITC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. 9325263 (Proceedings - International Test Conference; Vol. 2020-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Yang, Eric

PY - 2020/11/1

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N2 - We propose a framework to co-optimize Yield along with Power, Performance and Area (PPA) through the design flow from logic synthesis through placement and routing (APR). We accomplish this by learning from silicon using a combination of test/diagnosis, inline/metrology and Failure Analysis (FA) results to create predictive models using Machine Learning (ML) techniques that are then used during design. Simulation results across three different CPU and Graphics cores show promising results with projected yield improvements of 11-17% with no area and performance / timing penalty with respect to design targets but with tradeoffs to both static and dynamic power. Better joint exploration of the PPA space along with yield indicates it is possible to recover yield with close to iso-PPA with respect to design targets. Pre-silicon results show \sim 10.4% yield increase with iso-Area and-iso-performance and \sim 1% power penalty on a processor core.

AB - We propose a framework to co-optimize Yield along with Power, Performance and Area (PPA) through the design flow from logic synthesis through placement and routing (APR). We accomplish this by learning from silicon using a combination of test/diagnosis, inline/metrology and Failure Analysis (FA) results to create predictive models using Machine Learning (ML) techniques that are then used during design. Simulation results across three different CPU and Graphics cores show promising results with projected yield improvements of 11-17% with no area and performance / timing penalty with respect to design targets but with tradeoffs to both static and dynamic power. Better joint exploration of the PPA space along with yield indicates it is possible to recover yield with close to iso-PPA with respect to design targets. Pre-silicon results show \sim 10.4% yield increase with iso-Area and-iso-performance and \sim 1% power penalty on a processor core.

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ER -

Automating Design for Yield: Silicon Learning to Predictive Models and Design Optimization

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Keywords

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