Automated integration of dual-edge clocking for low-power operation in nanometer nodes

Keyphrases

• 40nm CMOS 25%
• Automated Design 25%
• Automated Integration 100%
• Benchmark Circuits 25%
• Clock Distribution 50%
• Clock Frequency 25%
• Clocking Scheme 25%
• CMOS Technology 25%
• Design Flow 50%
• Digital Systems 25%
• Dual Edge Triggered 100%
• Dual-edge 100%
• Fully Automated 25%
• Integrated Circuits 25%
• Low Power Operation 100%
• Perceived Complexity 25%
• Power Consumption 50%
• Proposed Design 25%
• Sequential Elements 25%
• Single Edge Triggered 50%
• Total Energy Consumption 25%

Computer Science

• Benchmark Circuit 33%
• Clock Distribution 66%
• Clock Frequency 33%
• Clocking Scheme 33%
• Digital System 33%
• Integrated Circuits 33%
• Power Consumption 100%
• Sequential Element 33%
• Straightforward Approach 33%