Automated Design For Yield Through Defect Tolerance

We advocate defect tolerant design to improve timing yield. A metric of defect tolerance is proposed, and an approach based on using defect tolerance metrics, derived for each cell in a library, to bias logic synthesis and automated placement and routing (APR) to achieve netlist-level defect tolerance is explored. We compare our proposed approach, in which the delays of cells are penalized in accordance with their defect vulnerability to two alternative approaches: 1) an approach in which the most defect vulnerable cells are removed from consideration during automated design, and 2) another that gains yield by frequency-push over-design. We measure timing yield based on modeling defects as cell delay increments and using static timing analysis to evaluate the various approaches. Simulation results show promising timing yield improvements, with one case showing about 9.5% timing yield increase with under 3% area and 2% power costs.