Abstract
We advocate defect tolerant design to improve timing yield. A metric of defect tolerance is proposed, and an approach based on using defect tolerance metrics, derived for each cell in a library, to bias logic synthesis and automated placement and routing (APR) to achieve netlist-level defect tolerance is explored. We compare our proposed approach, in which the delays of cells are penalized in accordance with their defect vulnerability to two alternative approaches: 1) an approach in which the most defect vulnerable cells are removed from consideration during automated design, and 2) another that gains yield by frequency-push over-design. We measure timing yield based on modeling defects as cell delay increments and using static timing analysis to evaluate the various approaches. Simulation results show promising timing yield improvements, with one case showing about 9.5% timing yield increase with under 3% area and 2% power costs.
Original language | English |
---|---|
Title of host publication | Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020 |
Publisher | IEEE Computer Society |
ISBN (Electronic) | 9781728153599 |
DOIs | |
State | Published - Apr 2020 |
Externally published | Yes |
Event | 38th IEEE VLSI Test Symposium, VTS 2020 - San Diego, United States Duration: 5 Apr 2020 → 8 Apr 2020 |
Publication series
Name | Proceedings of the IEEE VLSI Test Symposium |
---|---|
Volume | 2020-April |
Conference
Conference | 38th IEEE VLSI Test Symposium, VTS 2020 |
---|---|
Country/Territory | United States |
City | San Diego |
Period | 5/04/20 → 8/04/20 |
Bibliographical note
Publisher Copyright:© 2020 IEEE.
Keywords
- APR
- defect
- defect tolerance
- design-for-yield
- reliability
- synthesis
- timing
- yield