Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits

Mateo Rendón; Christian Cao; Kevin Landázuri; Luis Miguel Prócel; Lionel Trojman; Ramiro Taco

doi:10.1109/ETCM53643.2021.9590651

Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits

Mateo Rendón
, Christian Cao
, Kevin Landázuri
, Luis Miguel Prócel
, Lionel Trojman
, Ramiro Taco

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin are compared with 10 nm FinFETs for a wide voltage supply ranging from 200 to 600 mV with a specific focus on the ultra-low voltage domain. A calibration process is carried out to ensure the same off-current and extrinsic capacitance in both devices. The TFETs presented a high advantage in terms of delay as well as a penalty in energy consumed. As a result, the TFET circuits show a better Energy-Delay trade-off in voltages as low as 350 m V. This is explained by a larger capacitance caused by the nature of the intrinsic materials chosen of the device modelling.

Original language	English
Title of host publication	ETCM 2021 - 5th Ecuador Technical Chapters Meeting
Editors	Monica Karel Huerta, Sebastian Quevedo, Carlos Monsalve
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665441414
DOIs	https://doi.org/10.1109/ETCM53643.2021.9590651
State	Published - 12 Oct 2021
Externally published	Yes
Event	5th IEEE Ecuador Technical Chapters Meeting, ETCM 2021 - Cuenca, Ecuador Duration: 12 Oct 2021 → 15 Oct 2021

Publication series

Name	ETCM 2021 - 5th Ecuador Technical Chapters Meeting

Conference

Conference	5th IEEE Ecuador Technical Chapters Meeting, ETCM 2021
Country/Territory	Ecuador
City	Cuenca
Period	12/10/21 → 15/10/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Keywords

Digital circuits
Energy-delay trade-off
FinFET
Tunnel-FET (TFET)
Ultra-low voltage

Access to Document

10.1109/ETCM53643.2021.9590651

Cite this

Rendón, M., Cao, C., Landázuri, K., Prócel, L. M., Trojman, L., & Taco, R. (2021). Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits. In M. K. Huerta, S. Quevedo, & C. Monsalve (Eds.), ETCM 2021 - 5th Ecuador Technical Chapters Meeting (ETCM 2021 - 5th Ecuador Technical Chapters Meeting). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ETCM53643.2021.9590651

Rendón, Mateo ; Cao, Christian ; Landázuri, Kevin et al. / Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits. ETCM 2021 - 5th Ecuador Technical Chapters Meeting. editor / Monica Karel Huerta ; Sebastian Quevedo ; Carlos Monsalve. Institute of Electrical and Electronics Engineers Inc., 2021. (ETCM 2021 - 5th Ecuador Technical Chapters Meeting).

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title = "Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits",

abstract = "The trade-offs of the Tunnel-FETs (TFETs) in terms of delay, energy per cycle, and noise margin are compared with 10 nm FinFETs for a wide voltage supply ranging from 200 to 600 mV with a specific focus on the ultra-low voltage domain. A calibration process is carried out to ensure the same off-current and extrinsic capacitance in both devices. The TFETs presented a high advantage in terms of delay as well as a penalty in energy consumed. As a result, the TFET circuits show a better Energy-Delay trade-off in voltages as low as 350 m V. This is explained by a larger capacitance caused by the nature of the intrinsic materials chosen of the device modelling.",

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Rendón, M, Cao, C, Landázuri, K, Prócel, LM, Trojman, L & Taco, R 2021, Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits. in MK Huerta, S Quevedo & C Monsalve (eds), ETCM 2021 - 5th Ecuador Technical Chapters Meeting. ETCM 2021 - 5th Ecuador Technical Chapters Meeting, Institute of Electrical and Electronics Engineers Inc., 5th IEEE Ecuador Technical Chapters Meeting, ETCM 2021, Cuenca, Ecuador, 12/10/21. https://doi.org/10.1109/ETCM53643.2021.9590651

Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits. / Rendón, Mateo; Cao, Christian; Landázuri, Kevin et al.
ETCM 2021 - 5th Ecuador Technical Chapters Meeting. ed. / Monica Karel Huerta; Sebastian Quevedo; Carlos Monsalve. Institute of Electrical and Electronics Engineers Inc., 2021. (ETCM 2021 - 5th Ecuador Technical Chapters Meeting).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Rendón M, Cao C, Landázuri K, Prócel LM, Trojman L, Taco R. Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits. In Huerta MK, Quevedo S, Monsalve C, editors, ETCM 2021 - 5th Ecuador Technical Chapters Meeting. Institute of Electrical and Electronics Engineers Inc. 2021. (ETCM 2021 - 5th Ecuador Technical Chapters Meeting). doi: 10.1109/ETCM53643.2021.9590651

Assessment of 10 nm Tunnel-FETs and FinFETs transistors for ultra-low voltage and high-speed digital circuits

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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Cite this