Abstract
The limited size and power budgets of space-bound systems often contradict the requirements for reliable circuit operation within high-radiation environments. In this paper, we propose the smallest solution for soft-error tolerant embedded memory yet to be presented. The proposed complementary dual-modular redundancy (CDMR) memory is based on a four-transistor dynamic memory core that internally stores complementary data values to provide an inherent per-bit error detection capability. By adding simple, low-overhead parity, an error-correction capability is added to the memory architecture for robust soft-error protection. The proposed memory was implemented in a 65-nm CMOS technology, displaying as much as a 3.5×1 smaller silicon footprint than other radiation-hardened bitcells. In addition, the CDMR memory consumes between 48% and 87% less standby power than other considered solutions across the entire operating region.
| Original language | English |
|---|---|
| Pages (from-to) | 502-509 |
| Number of pages | 8 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 25 |
| Issue number | 2 |
| DOIs | |
| State | Published - Feb 2017 |
Bibliographical note
Publisher Copyright:© 1993-2012 IEEE.
Funding
Manuscript received March 31, 2016; revised July 3, 2016; accepted August 24, 2016. Date of publication September 8, 2016; date of current version January 19, 2017. This work was supported by the HiPer Consortium under the Magnet program of the office of the chief scientist in the Israeli Ministry of Economy.
| Funders | Funder number |
|---|---|
| Consortium For Ocean Leadership | |
| Ministry of Economy |
Keywords
- Embedded dynamic random access memory (eDRAM)
- gain cell
- low power
- radiation hardening
- single event upset (SEU)
- soft errors
- space applications
- static RAM (SRAM)