ANSI standard ISDN transceiver chip set

The authors describe a two-chip ISDN U-interface transceiver based on the American National Standards Institute (ANSI) 2B1Q line code. The two chips are the analog front-end (AFE) which performs the line interfacing and data conversion functions and the digital subscriber loop (DSL) processor which performs the algorithm-specific signal processing (ASSP) functions in the receive path and in addition, the control, maintenance, and access functions (CMA). The ASSP functions are decimation of the sigma-delta modulator output from the AFE, linear and nonlinear echo cancellation, automatic gain control, interpolation, decision feedback equalization, and timing recovery. The CMA provides access to the digital interface and performs functions such as wire polarity check, rate conversion, framing, cyclic redundancy code generation and check, scrambling and descrambling, activation-deactivation, and start-up control. Successful operation of prototype chip sets has been demonstrated in a laboratory environment for a 26-gauge cable of lengths up to 18,000 ft.