Anomalous kink effect in low-dimensional gate-recessed fully depleted soi mosfet at low temperature

Avi Karsenty; Avraham Chelly

doi:10.1142/S1793292015500939

Anomalous kink effect in low-dimensional gate-recessed fully depleted soi mosfet at low temperature

Avi Karsenty, Avraham Chelly

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Lev Academic Center

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

Nanoscale MOSFETs Gate-Recessed Channel (GRC) device with a silicon channel thickness (tSI) as low as 2.2 nm was first tested at room temperature for functionality check, and then tested at low temperature (77 K) for I-V characterizations. In spite of its FD-SOI nanoscale thickness, the GRC device has surprisingly exhibited a Kink Effect in the output characteristics at 77 K. The anomalous Kink Effect can be explained by the increase of the lateral electric field in the drain junction with the channel extension zone when lowering the temperature.

Original language	English
Article number	1550093
Journal	Nano
Volume	10
Issue number	7
DOIs	https://doi.org/10.1142/S1793292015500939
State	Published - 1 Oct 2015

Bibliographical note

Publisher Copyright:
© 2015 World Scientific Publishing Company.

Keywords

Nanoscale FD-SOI MOSFET
kink effect
low temperature

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10.1142/S1793292015500939

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title = "Anomalous kink effect in low-dimensional gate-recessed fully depleted soi mosfet at low temperature",

abstract = "Nanoscale MOSFETs Gate-Recessed Channel (GRC) device with a silicon channel thickness (tSI) as low as 2.2 nm was first tested at room temperature for functionality check, and then tested at low temperature (77 K) for I-V characterizations. In spite of its FD-SOI nanoscale thickness, the GRC device has surprisingly exhibited a Kink Effect in the output characteristics at 77 K. The anomalous Kink Effect can be explained by the increase of the lateral electric field in the drain junction with the channel extension zone when lowering the temperature.",

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N2 - Nanoscale MOSFETs Gate-Recessed Channel (GRC) device with a silicon channel thickness (tSI) as low as 2.2 nm was first tested at room temperature for functionality check, and then tested at low temperature (77 K) for I-V characterizations. In spite of its FD-SOI nanoscale thickness, the GRC device has surprisingly exhibited a Kink Effect in the output characteristics at 77 K. The anomalous Kink Effect can be explained by the increase of the lateral electric field in the drain junction with the channel extension zone when lowering the temperature.

AB - Nanoscale MOSFETs Gate-Recessed Channel (GRC) device with a silicon channel thickness (tSI) as low as 2.2 nm was first tested at room temperature for functionality check, and then tested at low temperature (77 K) for I-V characterizations. In spite of its FD-SOI nanoscale thickness, the GRC device has surprisingly exhibited a Kink Effect in the output characteristics at 77 K. The anomalous Kink Effect can be explained by the increase of the lateral electric field in the drain junction with the channel extension zone when lowering the temperature.

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Anomalous kink effect in low-dimensional gate-recessed fully depleted soi mosfet at low temperature

Abstract

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Keywords

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