Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

Avi Karsenty, Avraham Chelly

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) for I-V characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

Original languageEnglish
Article number609828
JournalActive and Passive Electronic Components
Volume2015
DOIs
StatePublished - 2015

Bibliographical note

Publisher Copyright:
© 2015 Avi Karsenty and Avraham Chelly.

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