An analog readout circuit for use in conjunction with the Planar-Hall-Effect Magnetic-Random-Access-Memory is presented. The non-volatile nature of this type of memory allows zero leakage during memory retention, allowing significant power saving. The circuit employs a novel technique for readout operation of memory bit-cells. The circuit uses chopping and switched-capacitor techniques for amplification of the low input signal as well as elimination of DC-offset and low-frequency noise. The binary nature of the data allows an area efficient implementation at the cost of linearity, which is less significant for memory readout applications. The proposed circuit was implemented in the TowerJazz 180nm CMOS process at a supply voltage of 1.8V, and can reliably sense input signals with amplitude of as low as 1mV.
|Original language||American English|
|Title of host publication||Faible Tension Faible Consommation (FTFC)|
|State||Published - 2014|