An ultra-low-power application-specific processor with sub-VT memories for compressed sensing

Jeremy Constantin; Ahmed Dogan; Oskar Andersson; Pascal Meinerzhagen; Joachim Rodrigues; David Atienza; Andreas Burg

doi:10.1007/978-3-642-45073-0_5

An ultra-low-power application-specific processor with sub-V_T memories for compressed sensing

Jeremy Constantin, Ahmed Dogan, Oskar Andersson, Pascal Meinerzhagen, Joachim Rodrigues, David Atienza, Andreas Burg

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Compressed sensing (CS) is a universal low-complexity data compression technique for signals that have a sparse representation in some domain. While CS data compression can be done both in the analog- and digital domain, digital implementations are often used on low-power sensor nodes, where an ultra-low-power (ULP) processor carries out the algorithm on Nyquist-rate sampled data. In such systems an energy-efficient implementation of the CS compression kernel is a vital ingredient to maximize battery lifetime. In this paper, we propose an application-specific instruction-set processor (ASIP) processor that has been optimized for CS data compression and for operation in the subthreshold (sub-V_T) regime. The design is equipped with specific sub-V_T capable standard-cell based memories, to enable low-voltage operation with low leakage. Our results show that the proposed ASIP accomplishes 62× speed-up and 11.6× power savings with respect to a straightforward CS implementation running on the baseline low-power processor without instruction set extensions.

Original language	English
Title of host publication	VLSI-SoC
Subtitle of host publication	From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Revised Selected Papers
Editors	Matthew R. Guthaus, Srinivas Katkoori, Ayse Coskun, Andreas Burg, Srinivas Katkoori, Ricardo Reis, Ricardo Reis, Andreas Burg, Ayse Coskun, Matthew Guthaus
Publisher	Springer New York LLC
Pages	88-106
Number of pages	19
ISBN (Print)	9783642450723
DOIs	https://doi.org/10.1007/978-3-642-45073-0_5
State	Published - 2013
Externally published	Yes
Event	20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012 - Santa Cruz, CA, United States Duration: 7 Oct 2012 → 10 Oct 2012

Publication series

Name	IFIP Advances in Information and Communication Technology
Volume	418
ISSN (Print)	1868-4238

Conference

Conference	20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012
Country/Territory	United States
City	Santa Cruz, CA
Period	7/10/12 → 10/10/12

Bibliographical note

Publisher Copyright:
© IFIP International Federation for Information Proessing 2013.

Keywords

Application-Specific instruction set processor
Compressed sensing
Instruction set extensions
Sub-V embedded memories
Sub-V operation
Ultra-Low-Power processor

Access to Document

10.1007/978-3-642-45073-0_5

Cite this

Constantin, J., Dogan, A., Andersson, O., Meinerzhagen, P., Rodrigues, J., Atienza, D., & Burg, A. (2013). An ultra-low-power application-specific processor with sub-V_T memories for compressed sensing. In M. R. Guthaus, S. Katkoori, A. Coskun, A. Burg, S. Katkoori, R. Reis, R. Reis, A. Burg, A. Coskun, & M. Guthaus (Eds.), VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Revised Selected Papers (pp. 88-106). (IFIP Advances in Information and Communication Technology; Vol. 418). Springer New York LLC. https://doi.org/10.1007/978-3-642-45073-0_5

Constantin, Jeremy ; Dogan, Ahmed ; Andersson, Oskar et al. / An ultra-low-power application-specific processor with sub-V_T memories for compressed sensing. VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Revised Selected Papers. editor / Matthew R. Guthaus ; Srinivas Katkoori ; Ayse Coskun ; Andreas Burg ; Srinivas Katkoori ; Ricardo Reis ; Ricardo Reis ; Andreas Burg ; Ayse Coskun ; Matthew Guthaus. Springer New York LLC, 2013. pp. 88-106 (IFIP Advances in Information and Communication Technology).

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title = "An ultra-low-power application-specific processor with sub-VT memories for compressed sensing",

abstract = "Compressed sensing (CS) is a universal low-complexity data compression technique for signals that have a sparse representation in some domain. While CS data compression can be done both in the analog- and digital domain, digital implementations are often used on low-power sensor nodes, where an ultra-low-power (ULP) processor carries out the algorithm on Nyquist-rate sampled data. In such systems an energy-efficient implementation of the CS compression kernel is a vital ingredient to maximize battery lifetime. In this paper, we propose an application-specific instruction-set processor (ASIP) processor that has been optimized for CS data compression and for operation in the subthreshold (sub-VT) regime. The design is equipped with specific sub-VT capable standard-cell based memories, to enable low-voltage operation with low leakage. Our results show that the proposed ASIP accomplishes 62× speed-up and 11.6× power savings with respect to a straightforward CS implementation running on the baseline low-power processor without instruction set extensions.",

keywords = "Application-Specific instruction set processor, Compressed sensing, Instruction set extensions, Sub-V embedded memories, Sub-V operation, Ultra-Low-Power processor",

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Constantin, J, Dogan, A, Andersson, O, Meinerzhagen, P, Rodrigues, J, Atienza, D & Burg, A 2013, An ultra-low-power application-specific processor with sub-V_T memories for compressed sensing. in MR Guthaus, S Katkoori, A Coskun, A Burg, S Katkoori, R Reis, R Reis, A Burg, A Coskun & M Guthaus (eds), VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Revised Selected Papers. IFIP Advances in Information and Communication Technology, vol. 418, Springer New York LLC, pp. 88-106, 20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, United States, 7/10/12. https://doi.org/10.1007/978-3-642-45073-0_5

An ultra-low-power application-specific processor with sub-V_T memories for compressed sensing. / Constantin, Jeremy; Dogan, Ahmed; Andersson, Oskar et al.
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Revised Selected Papers. ed. / Matthew R. Guthaus; Srinivas Katkoori; Ayse Coskun; Andreas Burg; Srinivas Katkoori; Ricardo Reis; Ricardo Reis; Andreas Burg; Ayse Coskun; Matthew Guthaus. Springer New York LLC, 2013. p. 88-106 (IFIP Advances in Information and Communication Technology; Vol. 418).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Constantin J, Dogan A, Andersson O, Meinerzhagen P, Rodrigues J, Atienza D et al. An ultra-low-power application-specific processor with sub-V_T memories for compressed sensing. In Guthaus MR, Katkoori S, Coskun A, Burg A, Katkoori S, Reis R, Reis R, Burg A, Coskun A, Guthaus M, editors, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Revised Selected Papers. Springer New York LLC. 2013. p. 88-106. (IFIP Advances in Information and Communication Technology). doi: 10.1007/978-3-642-45073-0_5