Abstract
This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The proposed test structure uses high density standard logic gates as detection circuit for sensing Single Event Transients (SETs) that are then forwarded to a skewed NAND-NOR readout chain which funnels all SET pulses while expanding the pulse width to ensure they reach the final triple modular redundant (TMR) counter. The proposed circuit is compact, has a scalable architecture based on a unit cell layout, and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.
Original language | English |
---|---|
Title of host publication | 2017 IEEE International Electron Devices Meeting, IEDM 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 39.3.1-39.3.4 |
ISBN (Electronic) | 9781538635599 |
DOIs | |
State | Published - 23 Jan 2018 |
Externally published | Yes |
Event | 63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States Duration: 2 Dec 2017 → 6 Dec 2017 |
Publication series
Name | Technical Digest - International Electron Devices Meeting, IEDM |
---|---|
ISSN (Print) | 0163-1918 |
Conference
Conference | 63rd IEEE International Electron Devices Meeting, IEDM 2017 |
---|---|
Country/Territory | United States |
City | San Francisco |
Period | 2/12/17 → 6/12/17 |
Bibliographical note
Publisher Copyright:© 2017 IEEE.
Funding
Acknowledgements: The authors would like to thank Dr. Heather Quinn at Los Alamos National Labs for her help with the neutron beam tests. This work was funded in part by the U.S. Government. The data analysis work was partially supported by the Defense Threat Reduction Agency under Basic Research Award No. HDTRA1-14-1-0042. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. Government.
Funders | Funder number |
---|---|
U.S. Government | |
Defense Threat Reduction Agency |