An SRAM-Based PUF with a Capacitive Digital Preselection for a 1E-9 Key Error Probability

In this paper, a novel architecture of an SRAM-based Physical Unclonable Function (PUF) whose unstable cells are identified and masked by a 'capacitive tilt' preselection test is proposed. During the preselection test, either one of the cross-coupled inverter nodes is loaded with a digitally controlled capacitance, which can tilt the PUF towards a '1' or a '0'. Any cell which maintains its value during this test is deemed stable. Each capacitor bank is shared between four PUF cells, such that the additional area required is only 20%. This test does not require precision analog voltages, as did previous tests, and can thus be implemented by the user during key enrollment. In a test-chip implementation in TSMC 65nm node, the preselection test identified and disqualified all the cells that were measured as unstable in 18 PUF arrays, of 800 bits each. An overall scheme for PUF stabilization is proposed, composed of two error-reductions steps, comprising Inner and Outer error control blocks. The outer error control is typically a BCH code, which guarantees a required key error rate. The inner error control can either be the proposed tilt test, a BCH code, or another error correction scheme. To maximize the ratio of reliable key bits to physical PUF cells, i.e., the overall PUF code rate, several solutions were analyzed. It is shown that in order to achieve a key error rate of 1E-9, the most efficient construction is a tilt test followed by BCH[184,128,15], with a PUF code rate of 0.49. In addition, the tilt test is more efficient in terms of power, area and execution time than the other inner error correction mechanisms. Therefore, this construction is not only efficient by its overall code rate, but also by its area and its power, and further, it enables a more lightweight BCH implementation for the outer code.