An Improved AB 2 C scheme for leakage power reduction in image sensors with on-chip memory

Static leakage power is the major component of power consumption in large arrays that operate at a low activity factor. ¿Smart¿ image sensors with advanced in-pixel functionality frequently include large on-chip memory arrays for storage of per-pixel data. These systems periodically transfer data from pixels to their corresponding memory bits in a serial access scheme with a relatively low activity factor. Recently, an Adaptive Bulk Biasing Control (AB2C) Scheme for leakage reduction in image sensors was presented. In this paper, we introduce an improved AB2C scheme that expands the functionality for on-chip memory leakage reduction, in addition to that of the image sensor. In the proposed system, a symmetric voltage distribution is applied around the active row, providing reverse body biasing on deactivated rows to reduce leakage. A test case circuit was implemented in a standard 90 nm TSMC process is presented, showing a static power reduction of 26%.