An equivalence-checking method for scheduling verification in high-level synthesis

Chandan Karfa; Dipankar Sarkar; Chittaranjan Mandal; Pramod Kumar

doi:10.1109/tcad.2007.913390

An equivalence-checking method for scheduling verification in high-level synthesis

Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal, Pramod Kumar

Indian Institute of Technology Kharagpur

Research output: Contribution to journal › Article › peer-review

69 Scopus citations

Abstract

A formal method for checking equivalence between a given behavioral specification prior to scheduling and the one produced by the scheduler is described. Finite state machine with data path (FSMD) models have been used to represent both the behaviors. The method consists of introducing cutpoints in one FSMD, visualizing its computations as concatenation of paths from cutpoints to cutpoints, and identifying equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs interchanged. Unlike many other reported techniques, this method is strong enough to work when path segments in the original behavior are merged, a common feature of scheduling. It is also capable of verifying several arithmetic transformations and many code-motion techniques employed during scheduling. Correctness and complexity of the method have been dealt with. Experimental results for several high-level synthesis benchmarks demonstrate the effectiveness of the method.

Original language	English
Article number	4391074
Pages (from-to)	556-569
Number of pages	14
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	27
Issue number	3
DOIs	https://doi.org/10.1109/tcad.2007.913390
State	Published - Mar 2008
Externally published	Yes

Bibliographical note

Funding Information:
Manuscript received April 5, 2007; revised July 21, 2007. This work was supported in part by MHRD (Grant F.26-14/2003.TS.V) and in part by MCIT (SMDP-II projet), Government of India. This paper was recommended by Associate Editor A. Kuehlmann.

Funding

Manuscript received April 5, 2007; revised July 21, 2007. This work was supported in part by MHRD (Grant F.26-14/2003.TS.V) and in part by MCIT (SMDP-II projet), Government of India. This paper was recommended by Associate Editor A. Kuehlmann.

Funders	Funder number
Ministry of Human Resource Development	F.26-14/2003

Keywords

Equivalence checking
Finite state machine with data path (FSMD) models
Formal verification
High-level synthesis (HLS)
Scheduling

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10.1109/tcad.2007.913390

Cite this

@article{3d0aaa56388048489f205383e3b02b57,

title = "An equivalence-checking method for scheduling verification in high-level synthesis",

abstract = "A formal method for checking equivalence between a given behavioral specification prior to scheduling and the one produced by the scheduler is described. Finite state machine with data path (FSMD) models have been used to represent both the behaviors. The method consists of introducing cutpoints in one FSMD, visualizing its computations as concatenation of paths from cutpoints to cutpoints, and identifying equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs interchanged. Unlike many other reported techniques, this method is strong enough to work when path segments in the original behavior are merged, a common feature of scheduling. It is also capable of verifying several arithmetic transformations and many code-motion techniques employed during scheduling. Correctness and complexity of the method have been dealt with. Experimental results for several high-level synthesis benchmarks demonstrate the effectiveness of the method.",

keywords = "Equivalence checking, Finite state machine with data path (FSMD) models, Formal verification, High-level synthesis (HLS), Scheduling",

author = "Chandan Karfa and Dipankar Sarkar and Chittaranjan Mandal and Pramod Kumar",

note = "Funding Information: Manuscript received April 5, 2007; revised July 21, 2007. This work was supported in part by MHRD (Grant F.26-14/2003.TS.V) and in part by MCIT (SMDP-II projet), Government of India. This paper was recommended by Associate Editor A. Kuehlmann.",

year = "2008",

month = mar,

doi = "10.1109/tcad.2007.913390",

language = "אנגלית",

volume = "27",

pages = "556--569",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - An equivalence-checking method for scheduling verification in high-level synthesis

AU - Karfa, Chandan

AU - Sarkar, Dipankar

AU - Mandal, Chittaranjan

AU - Kumar, Pramod

N1 - Funding Information: Manuscript received April 5, 2007; revised July 21, 2007. This work was supported in part by MHRD (Grant F.26-14/2003.TS.V) and in part by MCIT (SMDP-II projet), Government of India. This paper was recommended by Associate Editor A. Kuehlmann.

PY - 2008/3

Y1 - 2008/3

N2 - A formal method for checking equivalence between a given behavioral specification prior to scheduling and the one produced by the scheduler is described. Finite state machine with data path (FSMD) models have been used to represent both the behaviors. The method consists of introducing cutpoints in one FSMD, visualizing its computations as concatenation of paths from cutpoints to cutpoints, and identifying equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs interchanged. Unlike many other reported techniques, this method is strong enough to work when path segments in the original behavior are merged, a common feature of scheduling. It is also capable of verifying several arithmetic transformations and many code-motion techniques employed during scheduling. Correctness and complexity of the method have been dealt with. Experimental results for several high-level synthesis benchmarks demonstrate the effectiveness of the method.

AB - A formal method for checking equivalence between a given behavioral specification prior to scheduling and the one produced by the scheduler is described. Finite state machine with data path (FSMD) models have been used to represent both the behaviors. The method consists of introducing cutpoints in one FSMD, visualizing its computations as concatenation of paths from cutpoints to cutpoints, and identifying equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs interchanged. Unlike many other reported techniques, this method is strong enough to work when path segments in the original behavior are merged, a common feature of scheduling. It is also capable of verifying several arithmetic transformations and many code-motion techniques employed during scheduling. Correctness and complexity of the method have been dealt with. Experimental results for several high-level synthesis benchmarks demonstrate the effectiveness of the method.

KW - Equivalence checking

KW - Finite state machine with data path (FSMD) models

KW - Formal verification

KW - High-level synthesis (HLS)

KW - Scheduling

UR - http://www.scopus.com/inward/record.url?scp=39749172371&partnerID=8YFLogxK

U2 - 10.1109/tcad.2007.913390

DO - 10.1109/tcad.2007.913390

M3 - ???researchoutput.researchoutputtypes.contributiontojournal.article???

AN - SCOPUS:39749172371

SN - 0278-0070

VL - 27

SP - 556

EP - 569

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 3

M1 - 4391074

ER -

An equivalence-checking method for scheduling verification in high-level synthesis

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