An energy-efficient graphics processor in 14-nm Tri-Gate CMOS featuring integrated voltage regulators for fine-grain DVFS, Retentive Sleep, and VMIN optimization

Pascal A. Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav Vaidya; Ashwin Mendon; D. Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; Joseph Ryan; Chung Ching Peng; Somnath Paul; Sriram Vangal; Brando Perez Esparza; L. Cuellar; M. Woodman; Bala Iyer; Subramaniam Maiyuran; G. Chinya; Xiang Zou; Yuyun Liao; Krishnan Ravichandran; H. Wang; Muhammad M. Khellah; James W. Tschanz; Vivek De

doi:10.1109/jssc.2018.2875097

An energy-efficient graphics processor in 14-nm Tri-Gate CMOS featuring integrated voltage regulators for fine-grain DVFS, Retentive Sleep, and V_MIN optimization

Pascal A. Meinerzhagen
, Carlos Tokunaga
, Andres Malavasi
, Vaibhav Vaidya
, Ashwin Mendon
, D. Mathaikutty
, Jaydeep Kulkarni
, Charles Augustine
, Minki Cho
, Stephen T. Kim
, George E. Matthew
, Rinkle Jain
, Joseph Ryan
, Chung Ching Peng
, Somnath Paul
, Sriram Vangal
, Brando Perez Esparza
, L. Cuellar
, M. Woodman
, Bala Iyer

Subramaniam Maiyuran, G. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, H. Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De

Intel

Research output: Contribution to journal › Article › peer-review

22 Scopus citations

Abstract

Graphics workloads make highly dynamic use of resources such as execution units (EUs), and thus can benefit from fast, fine-grain dynamic voltage and frequency scaling (DVFS) and retentive sleep. This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an integrated voltage regulator (IVR). The IVR enables energy-efficient EU turbo operation, data retention, and V_MIN optimization per EU. Silicon measurements show that IVR-enabled EU turbo operation offers up to 32% (average 29%) energy reduction at constant performance.

Original language	English
Article number	8527541
Pages (from-to)	144-157
Number of pages	14
Journal	IEEE Journal of Solid-State Circuits
Volume	54
Issue number	1
DOIs	https://doi.org/10.1109/jssc.2018.2875097
State	Published - Jan 2019
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 1966-2012 IEEE.

Funding

Manuscript received May 9, 2018; revised July 27, 2018 and September 27, 2018; accepted September 28, 2018. Date of publication November 8, 2018; date of current version January 14, 2019. This paper was approved by Guest Editor Masato Motomura. This work was supported by the U.S. Government (DARPA). (Corresponding author: Pascal A. Meinerzhagen.) The authors are with Intel Corporation, Hillsboro, OR 97124 USA (e-mail: [email protected]).

Funders
U.S. Government
Defense Advanced Research Projects Agency

Keywords

Energy-efficient graphics processing unit (GPU)
VMIN optimization
fine-grain dynamic voltage and frequency scaling (DVFS)
integrated voltage regulators (IVRs)
retentive sleep

Access to Document

10.1109/jssc.2018.2875097

Cite this

Meinerzhagen, P. A., Tokunaga, C., Malavasi, A., Vaidya, V., Mendon, A., Mathaikutty, D., Kulkarni, J., Augustine, C., Cho, M., Kim, S. T., Matthew, G. E., Jain, R., Ryan, J., Peng, C. C., Paul, S., Vangal, S., Perez Esparza, B., Cuellar, L., Woodman, M., ... De, V. (2019). An energy-efficient graphics processor in 14-nm Tri-Gate CMOS featuring integrated voltage regulators for fine-grain DVFS, Retentive Sleep, and V_MIN optimization. IEEE Journal of Solid-State Circuits, 54(1), 144-157. Article 8527541. https://doi.org/10.1109/jssc.2018.2875097

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abstract = "Graphics workloads make highly dynamic use of resources such as execution units (EUs), and thus can benefit from fast, fine-grain dynamic voltage and frequency scaling (DVFS) and retentive sleep. This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an integrated voltage regulator (IVR). The IVR enables energy-efficient EU turbo operation, data retention, and VMIN optimization per EU. Silicon measurements show that IVR-enabled EU turbo operation offers up to 32\% (average 29\%) energy reduction at constant performance.",

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Meinerzhagen, PA, Tokunaga, C, Malavasi, A, Vaidya, V, Mendon, A, Mathaikutty, D, Kulkarni, J, Augustine, C, Cho, M, Kim, ST, Matthew, GE, Jain, R, Ryan, J, Peng, CC, Paul, S, Vangal, S, Perez Esparza, B, Cuellar, L, Woodman, M, Iyer, B, Maiyuran, S, Chinya, G, Zou, X, Liao, Y, Ravichandran, K, Wang, H, Khellah, MM, Tschanz, JW & De, V 2019, 'An energy-efficient graphics processor in 14-nm Tri-Gate CMOS featuring integrated voltage regulators for fine-grain DVFS, Retentive Sleep, and V_MIN optimization', IEEE Journal of Solid-State Circuits, vol. 54, no. 1, 8527541, pp. 144-157. https://doi.org/10.1109/jssc.2018.2875097

An energy-efficient graphics processor in 14-nm Tri-Gate CMOS featuring integrated voltage regulators for fine-grain DVFS, Retentive Sleep, and V_MIN optimization. / Meinerzhagen, Pascal A.; Tokunaga, Carlos; Malavasi, Andres et al.
In: IEEE Journal of Solid-State Circuits, Vol. 54, No. 1, 8527541, 01.2019, p. 144-157.

Research output: Contribution to journal › Article › peer-review

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AU - Vaidya, Vaibhav

AU - Mendon, Ashwin

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AU - Maiyuran, Subramaniam

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AU - Zou, Xiang

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