Graphics workloads make highly dynamic use of resources such as execution units (EUs), and thus can benefit from fast, fine-grain dynamic voltage and frequency scaling (DVFS) and retentive sleep. This paper presents a 14-nm graphics processing unit (GPU) prototype with modified EUs which include an integrated voltage regulator (IVR). The IVR enables energy-efficient EU turbo operation, data retention, and VMIN optimization per EU. Silicon measurements show that IVR-enabled EU turbo operation offers up to 32% (average 29%) energy reduction at constant performance.
Bibliographical noteFunding Information:
Manuscript received May 9, 2018; revised July 27, 2018 and September 27, 2018; accepted September 28, 2018. Date of publication November 8, 2018; date of current version January 14, 2019. This paper was approved by Guest Editor Masato Motomura. This work was supported by the U.S. Government (DARPA). (Corresponding author: Pascal A. Meinerzhagen.) The authors are with Intel Corporation, Hillsboro, OR 97124 USA (e-mail: firstname.lastname@example.org).
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- Energy-efficient graphics processing unit (GPU)
- VMIN optimization
- fine-grain dynamic voltage and frequency scaling (DVFS)
- integrated voltage regulators (IVRs)
- retentive sleep