An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS

Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen Kim, George Matthew, Rinkle Jain, Joseph Ryan, Chung Ching Peng, Somnath Paul, Sriram Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala IyerSubramaniam Maiyuran, Gautham Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad Khellah, James Tschanz, Vivek De

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

27 Scopus citations

Abstract

Graphics workloads are highly dynamic in nature, using multi-threaded SIMD execution units (EUs), fixed-function units, samplers, and media accelerators to provide ever-increasing amounts of graphics performance. These workloads are often limited by power and thermal constraints, requiring dynamic voltage/frequency scaling (DVFS) of the graphics processor (GPU). This coarse-grain DVFS, driven by a power-management IC (PMIC) setting a shared rail voltage (VIN), incurs performance loss while waiting for PLL re-lock and slow-rail voltage transitions. In addition, it does not allow a performance-critical unit (e.g. an EU) to use on demand a higher V/F (e.g. for EU turbo) without an energy penalty for the rest of the GPU.

Original languageEnglish
Title of host publication2018 IEEE International Solid-State Circuits Conference, ISSCC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages38-40
Number of pages3
ISBN (Electronic)9781509049394
DOIs
StatePublished - 8 Mar 2018
Externally publishedYes
Event65th IEEE International Solid-State Circuits Conference, ISSCC 2018 - San Francisco, United States
Duration: 11 Feb 201815 Feb 2018

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume61
ISSN (Print)0193-6530

Conference

Conference65th IEEE International Solid-State Circuits Conference, ISSCC 2018
Country/TerritoryUnited States
CitySan Francisco
Period11/02/1815/02/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Funding

The authors thank the many members of the Intel Labs circuit research, microarchitecture research, and silicon/system prototyping teams that contributed to this work, as well as the Intel Visual and Parallel Computing Group. This research was, in part, funded by the U.S. Government (DARPA). The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. Government.

FundersFunder number
U.S. Government
Defense Advanced Research Projects Agency

    Fingerprint

    Dive into the research topics of 'An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS'. Together they form a unique fingerprint.

    Cite this