An efficient implementation of D-Flip-Flop using the GDI technique

Arkadiy Morgenshtein, A. Fish, Israel A. Wagner

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


A new implementation of efficient D-Flip-Flop (DFF) using Gate-Diffusion-Input (GDI) technique is presented. This DFF design allows reducing power-delay product and area of the circuit, while maintaining low complexity of logic design. Performance comparison with other DFF design techniques is presented, with respect to gate area, number of devices, delay and power dissipation, showing advantages and drawbacks of GDI DFF, as compared to other methods. A variety of circuits have been implemented in 0.35 μm and 0.1 μm technologies to compare the proposed GDI structure with existing alternatives, showing an up-to 45% reduction in power-delay product in GDI. Properties of implemented circuit are discussed and simulation results are reported.
Original languageAmerican English
Title of host publicationCircuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
StatePublished - 2004

Bibliographical note

Place of conference:Canada


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