TY - GEN
T1 - An efficient implementation of D-Flip-Flop using the GDI technique
AU - Morgenshtein, Arkadiy
AU - Fish, A.
AU - Wagner, Israel A.
N1 - Place of conference:Canada
PY - 2004
Y1 - 2004
N2 - A new implementation of efficient D-Flip-Flop (DFF) using Gate-Diffusion-Input (GDI) technique is presented. This DFF design allows reducing power-delay product and area of the circuit, while maintaining low complexity of logic design. Performance comparison with other DFF design techniques is presented, with respect to gate area, number of devices, delay and power dissipation, showing advantages and drawbacks of GDI DFF, as compared to other methods. A variety of circuits have been implemented in 0.35 μm and 0.1 μm technologies to compare the proposed GDI structure with existing alternatives, showing an up-to 45% reduction in power-delay product in GDI. Properties of implemented circuit are discussed and simulation results are reported.
AB - A new implementation of efficient D-Flip-Flop (DFF) using Gate-Diffusion-Input (GDI) technique is presented. This DFF design allows reducing power-delay product and area of the circuit, while maintaining low complexity of logic design. Performance comparison with other DFF design techniques is presented, with respect to gate area, number of devices, delay and power dissipation, showing advantages and drawbacks of GDI DFF, as compared to other methods. A variety of circuits have been implemented in 0.35 μm and 0.1 μm technologies to compare the proposed GDI structure with existing alternatives, showing an up-to 45% reduction in power-delay product in GDI. Properties of implemented circuit are discussed and simulation results are reported.
UR - https://scholar.google.co.il/scholar?q=An+efficient+implementation+of+D-FLIP-FLOP+using+the+GDI+technique+&btnG=&hl=en&as_sdt=0%2C5
M3 - Conference contribution
BT - Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
PB - IEEE
ER -