An effective technique for simultaneous interconnect channel delay and noise reduction in nanometer VLSI design

Keyphrases

• Noise Reduction 100%
• Cross Capacitance 100%
• Nanometer Technology 100%
• Delay Reduction 100%
• Channel Noise 100%
• Effective Techniques 100%
• VLSI Design 100%
• Delay Uncertainty 100%
• Channel Delay 100%
• Two-parameter 50%
• Elmore Delay Model 50%
• Metal Layer 50%
• Parallel Wire 50%
• Single Metal 50%
• Delay Optimization 50%
• Interconnect Delay 50%
• Noise Voltage 50%
• Peak Noise 50%
• Delay Minimization 50%
• Time Characteristics 50%
• Crosstalk Noise 50%
• Capacitive Crosstalk 50%
• Noise Metrics 50%
• VLSI Circuits 50%
• Capacitive Coupling 50%
• CMOS VLSI 50%
• Noise Source 50%
• Uncertainty Optimization 50%
• Technology Scaling 50%
• Digital CMOS 50%
• Noise Minimization 50%

Computer Science

• Elmore Delay Model 100%
• Delay Minimization 100%
• Peak Noise Voltage 100%
• Interconnect Delay 100%
• Capacitive Coupling 100%

Engineering

• Interconnects 100%
• Nanometre 100%
• Crosstalk 50%
• Capacitive 25%
• Peak Noise 25%
• Capacitive Coupling 25%
• VLSI Circuits 25%
• Metal Layer 25%
• Noise Voltage 25%
• Metrics 25%