An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] dual-mode logic 8 × 8 bit multiplier accumulator with a self-adjustment mechanism in 28-nm FD-SOI

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

Research output: Contribution to journalArticlepeer-review

29 Scopus citations

Abstract

The unique ability of dual-mode logic (DML) to self-adapt to computational needs by providing high speed and/or low energy consumption is demonstrated for the first time by silicon measurements in 28-nm fully depleted silicon on insulator. At the gate level, the DML design offers the possibility to operate either in the static mode to save energy or in the dynamic mode to increase speed, albeit with higher delay or energy consumption, respectively. In this paper, these two operational modes of the DML gates are optimally managed by a self-adjustment mechanism to increase speed or reduce the energy of gates/blocks in the design at run time. As a test case, a two-stage pipelined multiply-accumulate (MAC) circuit was selected to assess the advantages of DML in terms of speed, energy, and area as compared to a conventional CMOS design. We show that the self-adjusted DML MAC achieves both a performance boost of up to 92% and 16% less energy consumption than the equivalent standard CMOS implementation. The energy saved can be even greater (up to 35%) when the low-power (fully static) mode is enabled. In addition, the DML MAC occupies 25% less area.

Original languageEnglish
Article number8574058
Pages (from-to)560-568
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number2
DOIs
StatePublished - Feb 2019

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

  • Dual-mode logic (DML)
  • high-speed
  • low-power
  • self-adaptive multiply-accumulate (MAC)

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