An 800-MHz Mixed-VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications

Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman

Research output: Contribution to journalArticlepeer-review

33 Scopus citations


Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional static random access memory (SRAM) due to its high-density, low-leakage, and inherent two-ported operation, yet its dynamic nature leads to limited retention time and calls for periodic, power-hungry refresh cycles. This drawback is further aggravated in scaled technologies, where increased leakage currents and decreased in-cell storage capacitances lead to accelerated data integrity deterioration. The emerging approximate computing paradigm utilizes the inherent error-resilience of different applications to tolerate some errors in the stored data. Such error tolerance can be exploited to reduce the refresh rate in GC-eDRAM to achieve a substantial decrease in power consumption at the cost of an increase in cell failure probability. In this paper, we present the first fabricated and fully functional GC-eDRAM in a 28-nm bulk CMOS technology. The array, which is based on a novel mixed- VT four-transistor (4T) gain cell with internal feedback (IFGC) optimized for high performance, features a small silicon footprint and supports high-performance operation. The proposed memory can be used with conservative (i.e., 100% reliable) computing paradigms, but also in the context of approximate computing, featuring a small silicon footprint and random access bandwidth. Silicon measurements demonstrate successful operation at 800 MHz under a 900-mv supply while retaining between 30% and 45% lower bitcell area than a single-ported six-transistor (6T) SRAM and a two-ported six-transistor (8T) SRAM in the same technology.

Original languageEnglish
Pages (from-to)2136-2148
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Issue number7
StatePublished - Jul 2018

Bibliographical note

Funding Information:
Manuscript received November 29, 2017; revised February 15, 2018 and March 18, 2018; accepted March 18, 2018. Date of publication May 8, 2018; date of current version June 25, 2018. This paper was approved by Guest Editor Shidhartha Das. This work was supported by the HiPer Consortium through the Israeli Innovation Authority. (Corresponding author: Robert Giterman.) R. Giterman, A. Fish, and A. Teman are with Emerging Nanoscaled Integrated Circuits and Systems Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan 5290002, Israel (e-mail:;;

Publisher Copyright:
© 2018 IEEE.


  • Approximate computing
  • gain cell
  • gain cell with internal feedback (IFGC)
  • gain-cell embedded DRAM (GC-eDRAM)
  • logic-compatible eDRAM
  • low power
  • static random access memory (SRAM)


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