An 800 Mhz Mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications

Robert Giterman; Alexander Fish; Narkis Geuli; Elad Mentovich; Andreas Burg; Adam Teman

doi:10.1109/esscirc.2017.8094587

An 800 Mhz Mixed-V_T 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications

Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional SRAM, due to its high-density, low-leakage, and inherent 2-ported operation, yet, its dynamic nature leads to limited retention time that requires periodic, power-hungry refresh cycles. This drawback is further aggravated in scaled technologies, where increased leakage currents and decreased in-cell storage capacitances lead to accelerated data integrity deterioration. However, the emerging approximate computing paradigm utilizes the inherent error resilience of some applications to tolerate data errors. Such error tolerance can be exploited by reducing the refresh rate in GC-eDRAM to achieve a substantial decrease in power consumption, at the cost of an increase in cell failure probability. In this paper, we present the first fabricated and fully functional GC-eDRAM in a 28nm bulk CMOS technology. The array, which is based on a novel mixed-V_T 4T bitcell, can be used in both traditional and for approximate computing applications, featuring a small silicon footprint and supporting high-performance operation. Silicon measurements demonstrate successful operation at 800 Mhz under a 900 mV supply, while retaining almost 30% lower area than a singleported 6T SRAM in the same technology.

Original language	English
Title of host publication	ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	308-311
Number of pages	4
ISBN (Electronic)	9781509050253
DOIs	https://doi.org/10.1109/esscirc.2017.8094587
State	Published - 2 Nov 2017
Event	43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017 - Leuven, Belgium Duration: 11 Sep 2017 → 14 Sep 2017

Publication series

Name	ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference

Conference

Conference	43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017
Country/Territory	Belgium
City	Leuven
Period	11/09/17 → 14/09/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Funding

V. CONCLUSIONS Approximate storage offers a compromise between improved memory density and power to decreased reliability, which can be tolerated by approximate computing applications. We demonstrated a novel mixed-VT 4T gain-cell implementation in a 28 nm logic process. The memory macro operates at a 800 Mhz frequency, more than any other gain-cell implementation in literature. Moreover, it provides almost 30% lower area compared to a conventional, single-ported, SRAM. The array can be operated with a 5 µs retention time with a 99% yield, suitable for approximate storage systems. Technology scaling to below 20 nm process nodes can be beneficial for the proposed GC-eDRAM technology as enhanced control of the channel using FD-SOI or FinFET technologies can result in lower sub-VT leakage and higher DRT. Moreover, “pushed-rules” layout of the GC-eDRAM bit-cell will result in even higher area savings. ACKNOWLEDGEMENT The authors would like to thank Yaniv Strassberg, Idan Hashai, Keren Talisveyberg, Ofer Shalev, Roy Kauffman, Ilan Braun, Omer Eini, and Roman Golman for their help in the design and measurements of the test-chip. This work was supported by the HiPer Consortium funded by the Israeli Innovation Authority.

Funders	Funder number
HiPer Consortium
Israeli Innovation Authority

Access to Document

10.1109/esscirc.2017.8094587

Cite this

Giterman, R., Fish, A., Geuli, N., Mentovich, E., Burg, A., & Teman, A. (2017). An 800 Mhz Mixed-V_T 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. In ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference (pp. 308-311). Article 8094587 (ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/esscirc.2017.8094587

Giterman, Robert ; Fish, Alexander ; Geuli, Narkis et al. / An 800 Mhz Mixed-V_T 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 308-311 (ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference).

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Giterman, R, Fish, A, Geuli, N, Mentovich, E, Burg, A & Teman, A 2017, An 800 Mhz Mixed-V_T 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference., 8094587, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 308-311, 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017, Leuven, Belgium, 11/09/17. https://doi.org/10.1109/esscirc.2017.8094587

An 800 Mhz Mixed-V_T 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. / Giterman, Robert; Fish, Alexander; Geuli, Narkis et al.
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2017. p. 308-311 8094587 (ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Giterman R, Fish A, Geuli N, Mentovich E, Burg A, Teman A. An 800 Mhz Mixed-V_T 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. In ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2017. p. 308-311. 8094587. (ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference). doi: 10.1109/esscirc.2017.8094587