TY - GEN
T1 - Amalgamated q-ary codes for multi-level flash memories
AU - Manzor, Yifat
AU - Keren, Osnat
PY - 2012
Y1 - 2012
N2 - A flash memory is a non-volatile memory based on electron storing mechanism. A multi-level flash memory cell can store one of q symbols (q > 2). As q increases, the data becomes less reliable and the probability it may be distorted by different types of errors increases. This paper presents an amalgamated q-ary code capable of correcting a mixture of ts symmetric errors and additional ta asymmetric errors of limited magnitude l. In the proposed code, each q-ary codeword is composed of n multi-bit symbols, each multi-bit (i.e. q-ary) symbol is viewed as two sub-symbols over two different alphabets. The new construction has higher code rate than the conventional single-alphabet code.
AB - A flash memory is a non-volatile memory based on electron storing mechanism. A multi-level flash memory cell can store one of q symbols (q > 2). As q increases, the data becomes less reliable and the probability it may be distorted by different types of errors increases. This paper presents an amalgamated q-ary code capable of correcting a mixture of ts symmetric errors and additional ta asymmetric errors of limited magnitude l. In the proposed code, each q-ary codeword is composed of n multi-bit symbols, each multi-bit (i.e. q-ary) symbol is viewed as two sub-symbols over two different alphabets. The new construction has higher code rate than the conventional single-alphabet code.
UR - http://www.scopus.com/inward/record.url?scp=84872337332&partnerID=8YFLogxK
U2 - 10.1109/dft.2012.6378207
DO - 10.1109/dft.2012.6378207
M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???
AN - SCOPUS:84872337332
SN - 9781467330428
T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SP - 98
EP - 103
BT - Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012
T2 - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012
Y2 - 3 October 2012 through 5 October 2012
ER -