TY - JOUR
T1 - All-optical linear reconfigurable logic with nonlinear phase erasure
AU - Nazarathy, Moshe
AU - Zalevsky, Zeev
AU - Rudnitsky, Arkady
AU - Larom, Bar
AU - Nevet, Amir
AU - Orenstein, Meir
AU - Fischer, Baruch
PY - 2009/8/1
Y1 - 2009/8/1
N2 - We introduce a novel all-optical logic architecture whereby the gates may be readily reconfigured to reprogram their logic to implement (N)AND/(N)OR/X(N)OR. A single gate structure may be used throughout the logic circuit to implement multiple truth tables. The reconfiguration is effected by an optical reference signal. The reference may also be adapted to an arbitrary Boolean complex alphabet at the gate logic inputs and calibrated to correct gate imperfections. The all-optical gate structure is partitioned into a linear interferometric front end and a nonlinear back end. In the linear section, two optical logic inputs, along with a reference signal, linearly interfere. The nonlinear back end realizes a phase-erasure (or phase-reset) function. The reconfiguration and recalibration capabilities, along with the functional decoupling between the linear and nonlinear sections of each gate, facilitate the potential aggregation of large gate counts into logic arrays. A fundamental lower bound for the expended energy per gate is derived as 3hv+kT In 2 Joules per bit.
AB - We introduce a novel all-optical logic architecture whereby the gates may be readily reconfigured to reprogram their logic to implement (N)AND/(N)OR/X(N)OR. A single gate structure may be used throughout the logic circuit to implement multiple truth tables. The reconfiguration is effected by an optical reference signal. The reference may also be adapted to an arbitrary Boolean complex alphabet at the gate logic inputs and calibrated to correct gate imperfections. The all-optical gate structure is partitioned into a linear interferometric front end and a nonlinear back end. In the linear section, two optical logic inputs, along with a reference signal, linearly interfere. The nonlinear back end realizes a phase-erasure (or phase-reset) function. The reconfiguration and recalibration capabilities, along with the functional decoupling between the linear and nonlinear sections of each gate, facilitate the potential aggregation of large gate counts into logic arrays. A fundamental lower bound for the expended energy per gate is derived as 3hv+kT In 2 Joules per bit.
UR - http://www.scopus.com/inward/record.url?scp=68849089497&partnerID=8YFLogxK
U2 - 10.1364/josaa.26.000a21
DO - 10.1364/josaa.26.000a21
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SN - 1084-7529
VL - 26
SP - A21-A39
JO - Journal of the Optical Society of America A: Optics and Image Science, and Vision
JF - Journal of the Optical Society of America A: Optics and Image Science, and Vision
IS - 8
ER -