TY - JOUR
T1 - All-analog decoder for a binary (18,9,5) tail-biting trellis code
AU - Lustenberger, Felix
AU - Helfenstein, Markus
AU - Moschytz, George S.
AU - Loeliger, Hans Andrea
AU - Tarköy, Felix
PY - 1999
Y1 - 1999
N2 - An all-analog high-speed decoding technique is described which is suitable for magnetic recording (MR) and other computationally demanding applications. A decoder for a binary (18,9,5) tail-biting trellis code, which is much simpler than the codes used for MR, has been chosen to demonstrate this technique. It achieves a decoding rate of 100 Mbit/s at a single 5V power supply. The power consumption is 50mW. Higher speed can essentially be traded for higher power consumption. A comparison shows that a digital implementation is outperformed by more than two orders of magnitude in terms of speed and/or power consumption.
AB - An all-analog high-speed decoding technique is described which is suitable for magnetic recording (MR) and other computationally demanding applications. A decoder for a binary (18,9,5) tail-biting trellis code, which is much simpler than the codes used for MR, has been chosen to demonstrate this technique. It achieves a decoding rate of 100 Mbit/s at a single 5V power supply. The power consumption is 50mW. Higher speed can essentially be traded for higher power consumption. A comparison shows that a digital implementation is outperformed by more than two orders of magnitude in terms of speed and/or power consumption.
UR - http://www.scopus.com/inward/record.url?scp=84893737448&partnerID=8YFLogxK
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AN - SCOPUS:84893737448
SN - 1930-8833
SP - 362
EP - 365
JO - European Solid-State Circuits Conference
JF - European Solid-State Circuits Conference
M1 - 1471171
T2 - 25th European Solid-State Circuits Conference, ESSCIRC 1999
Y2 - 21 September 1999 through 23 September 1999
ER -