In the design of custom VLSI chips for digital signal processing (DSP) applications, a good algorithm-architecture mapping is critical to achieve efficiency and high performance. It is shown how an efficient mapping can be derived not only by adapting an architecture to a given algorithm, but also by changing the algorithm's description in a systematic way. A tool under development to support the designer in this procedure is described. Its graphical interface allows a flexible description of the algorithm. The tool can be used on different hierarchy levels and is capable of working on a combination of levels (mixed levels) as well. Besides these algorithm transformations, it performs the simulation of algorithms and scheduling of DSP algorithms on parallel hardware architectures.