Accurate quantitative physics-of-failure approach to integrated circuit reliability

Edward Wyrwas, Lloyd Condra, Avshalom Hava

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs, ADCs, and memory. They are susceptible to electrical, mechanical and thermal modes of failure like other components on a printed circuit board, but due to their materials, complexity and roles within a circuit, accurately predicting a failure rate has become difficult, if not impossible. Development of these critical components has conformed to Moore's Law, where the number of transistors on a die doubles approximately every two years. This trend has been successfully followed over the last four decades through reduction in transistor sizes creating faster, smaller ICs with greatly reduced power dissipation. Although this is great news for developers and users of high performance equipment, including consumer products and analytical instrumentation, a crucial, yet underlying reliability risk has emerged. Semiconductor failure mechanisms, which are far worse at these minute feature sizes (tens of nanometers), result in higher failure rates, shorter device lifetimes and unanticipated early device wearout. This is of special concern to users whose requirements include long service lifetimes and rugged environmental conditions, such as aerospace, defense, and other high performance (ADHP) industries. To that end, the Aerospace Vehicle Systems Institute (AVSI) has conducted research in this area, and DfR Solutions has performed much of the work as a contractor to AVSI. Physics-of-Failure (PoF) knowledge and an accurate mathematical approach which utilizes semiconductor formulae, industry accepted failure mechanism models, and device functionality can access reliability of those integrated circuits vital to system stability. Currently, four semiconductor failure mechanisms that exist in silicon-based ICs are analyzed: Electromigration (EM), Time Dependent Dielectric Breakdown (TDDB), Hot Carrier Injection (HCI), and Negative Bias Temperature Instability (NBTI). Mitigation of these inherent failure mechanisms, including those considered wearout, is possible only when reliability can be quantified. Algorithms have been folded into a software application not only to calculate a failure rate, but also to produce confidence intervals and lifetime curves, using both steady state and wearout failure rates, for the IC under analysis. The algorithms have been statistically verified through testing and employ data and formulae from semiconductor materials (including technology node parameters), circuit fundamentals, transistor behavior, circuit design and fabrication processes. Initial development has yielded a user friendly software module with the ability to address siliconbased integrated circuits of the 0.35μm, 0.25μm, 0.18μm, 0.13μm and 90nm technology nodes.

Original languageEnglish
Title of host publicationIPC APEX EXPO Technical Conference 2011
Pages1776-1815
Number of pages40
StatePublished - 2011
Externally publishedYes
EventIPC APEX EXPO Technical Conference 2011 - Las Vegas, NV, United States
Duration: 12 Apr 201114 Apr 2011

Publication series

NameIPC APEX EXPO Technical Conference 2011
Volume3

Conference

ConferenceIPC APEX EXPO Technical Conference 2011
Country/TerritoryUnited States
CityLas Vegas, NV
Period12/04/1114/04/11

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