A transient noise analysis of secured dual-rail based logic style

Kashif Nawaz, Itamar Levi, Francois Xavier Standaert, Denis Flandre

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Dual-rail logic circuits have been used as an effective countermeasure towards a more secure circuit design. However, with technology scaling and lowering of V DD , they lose interest as the signal reduction is less significant compared to CMOS. In this work, we revisit dual-rail logic designs (more specifically DDSLL) while focusing on intrinsic physical device noise using a transient noise analysis methodology and show that there exists a potential for such circuits to reduce the signal and concretely increase the noise. Our analysis, which extends to meaningful cryptographic figures-of-merit (FoMs) such as the SNR (Signal-to-Noise ratio) and Mutual-Information (MI), better clarifies the potential of DDSLL circuits to leverage the noise.

Original languageEnglish
Title of host publication2018 New Generation of CAS, NGCAS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages146-149
Number of pages4
ISBN (Electronic)9781538676813
DOIs
StatePublished - 10 Dec 2018
Externally publishedYes
Event2018 New Generation of CAS, NGCAS 2018 - Valletta, Malta
Duration: 20 Nov 201823 Nov 2018

Publication series

Name2018 New Generation of CAS, NGCAS 2018

Conference

Conference2018 New Generation of CAS, NGCAS 2018
Country/TerritoryMalta
CityValletta
Period20/11/1823/11/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

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