The increasing impact of variability on near-threshold nanometer circuits calls for a tighter online monitoring and control of the available timing margins. Error-detection sequentials are widely used together with error-correction techniques to operate digital designs with such carefully controlled far-below-worst-case margins, ensuring their correct operation even in the presence of uncertainties and variations. However, these registers are often designed only to either detect setup timing violations or to measure the available positive timing slack for a small detection-window. In this paper we propose a timing-monitoring sequential that provides both timing-monitoring modes, which can be selected at run-time depending on the desired timing-monitoring strategy. As the detection window of the presented circuit depends on the duty-cycle of the clock, either slow paths or fast paths can be monitored and measured with wide timing windows. The performance of this timing-monitoring sequential is evaluated in a 28 nm FD-SOI process with post-layout simulations which show that the circuit is able to monitor a positive timing slack as small as 140 ps or to measure a path delay as fast as 50 ps. The proposed circuit is applied to a digital multiplier that was fabricated in a test chip and measurements show that the timing-monitoring sequentials are able to measure the critical path of the multiplier with a 1% accuracy and without incurring any timing violation.
|Title of host publication||2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - 26 Apr 2018|
|Event||2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy|
Duration: 27 May 2018 → 30 May 2018
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Conference||2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018|
|Period||27/05/18 → 30/05/18|
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