A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS

A. Mishra; A. J. Raymond; L. G. Amaru; G. Sarkis; C. Leroux; P. Meinerzhagen; A. Burg; W. J. Gross

doi:10.1109/ipec.2012.6522661

A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS

A. Mishra, A. J. Raymond, L. G. Amaru, G. Sarkis, C. Leroux, P. Meinerzhagen, A. Burg, W. J. Gross

Research output: Contribution to conference › Paper › peer-review

74 Scopus citations

Abstract

This paper presents the first ASIC implementation of a successive cancellation (SC) decoder for polar codes. The implemented ASIC relies on a semi-parallel architecture where processing resources are reused to achieve good hardware efficiency. A speculative decoding technique is employed to increase the throughput by 25% at the cost of very limited added complexity. The resulting architecture is implemented in a 180nm technology. The fabricated chip can be clocked at 150 MHz and uses 183k gates. It was verified using an FPGA testing setup and provides reference for the true silicon complexity of SC decoders for polar codes.

Original language	English
Pages	205-208
Number of pages	4
DOIs	https://doi.org/10.1109/ipec.2012.6522661
State	Published - 2012
Externally published	Yes
Event	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan Duration: 12 Nov 2012 → 14 Nov 2012

Conference

Conference	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
Country/Territory	Japan
City	Kobe
Period	12/11/12 → 14/11/12

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10.1109/ipec.2012.6522661

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abstract = "This paper presents the first ASIC implementation of a successive cancellation (SC) decoder for polar codes. The implemented ASIC relies on a semi-parallel architecture where processing resources are reused to achieve good hardware efficiency. A speculative decoding technique is employed to increase the throughput by 25\% at the cost of very limited added complexity. The resulting architecture is implemented in a 180nm technology. The fabricated chip can be clocked at 150 MHz and uses 183k gates. It was verified using an FPGA testing setup and provides reference for the true silicon complexity of SC decoders for polar codes.",

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AU - Sarkis, G.

AU - Leroux, C.

AU - Meinerzhagen, P.

AU - Burg, A.

AU - Gross, W. J.

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AB - This paper presents the first ASIC implementation of a successive cancellation (SC) decoder for polar codes. The implemented ASIC relies on a semi-parallel architecture where processing resources are reused to achieve good hardware efficiency. A speculative decoding technique is employed to increase the throughput by 25% at the cost of very limited added complexity. The resulting architecture is implemented in a 180nm technology. The fabricated chip can be clocked at 150 MHz and uses 183k gates. It was verified using an FPGA testing setup and provides reference for the true silicon complexity of SC decoders for polar codes.

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A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS

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