TY - GEN
T1 - A sub-VT 2T gain-cell memory for biomedical applications
AU - Meinerzhagen, Pascal
AU - Teman, Adam
AU - Mordakhay, Anatoli
AU - Burg, Andreas
AU - Fish, Alexander
PY - 2012
Y1 - 2012
N2 - Biomedical systems often require several kb of embedded memory and are typically operated in the subthreshold (sub-VT) domain for good energy-efficiency. Embedded memories and their leakage current can easily dominate the overall silicon area and the total power consumption, respectively. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. For the first time, this paper presents a gain-cell array which is fully functional in the sub-VT regime and achieves a data retention time that is more than 104 times higher than the access time. Monte Carlos simulations show that the 2 kb gain-cell array, implemented in a mature 0.18μm CMOS node and supplied with a sub-VT voltage of 400mV, exhibits robust write and read operations at 500 kHz under parametric variations and has over 99% availibilty for read and write access.
AB - Biomedical systems often require several kb of embedded memory and are typically operated in the subthreshold (sub-VT) domain for good energy-efficiency. Embedded memories and their leakage current can easily dominate the overall silicon area and the total power consumption, respectively. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. For the first time, this paper presents a gain-cell array which is fully functional in the sub-VT regime and achieves a data retention time that is more than 104 times higher than the access time. Monte Carlos simulations show that the 2 kb gain-cell array, implemented in a mature 0.18μm CMOS node and supplied with a sub-VT voltage of 400mV, exhibits robust write and read operations at 500 kHz under parametric variations and has over 99% availibilty for read and write access.
UR - http://www.scopus.com/inward/record.url?scp=84873542917&partnerID=8YFLogxK
U2 - 10.1109/SubVT.2012.6404318
DO - 10.1109/SubVT.2012.6404318
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AN - SCOPUS:84873542917
SN - 9781467315876
T3 - 2012 IEEE Subthreshold Microelectronics Conference, SubVT 2012
BT - 2012 IEEE Subthreshold Microelectronics Conference, SubVT 2012
T2 - 2012 IEEE Subthreshold Microelectronics Conference, SubVT 2012
Y2 - 9 October 2012 through 10 October 2012
ER -