A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications

Robert Giterman; Adam Teman; Lior Atias; Alexander Fish

doi:10.1109/S3S.2015.7333525

A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications

Robert Giterman
, Adam Teman
, Lior Atias
, Alexander Fish

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Swiss Federal Institute of Technology Lausanne

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Embedded memories often constitute over 50% of the total silicon area and are the main consumer of static power in ultra-low power (ULP) applications. Operation at sub-threshold supply voltages can significantly reduce the power dissipation of memory arrays, however it also results in lower noise margins and much higher susceptibility to radiation effects, such as soft errors or single event upsets (SEU).

Original language	English
Title of host publication	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509002597
DOIs	https://doi.org/10.1109/S3S.2015.7333525
State	Published - 20 Nov 2015
Event	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, United States Duration: 5 Oct 2015 → 8 Oct 2015

Publication series

Name	2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Conference

Conference	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
Country/Territory	United States
City	Rohnert Park
Period	5/10/15 → 8/10/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

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10.1109/S3S.2015.7333525

Cite this

Giterman, R., Teman, A., Atias, L., & Fish, A. (2015). A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 Article 7333525 (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2015.7333525

Giterman, Robert ; Teman, Adam ; Atias, Lior et al. / A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications. 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

@inproceedings{f2a4ea9bc1be4798bf3aa4d1b55ef79e,

title = "A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications",

abstract = "Embedded memories often constitute over 50\% of the total silicon area and are the main consumer of static power in ultra-low power (ULP) applications. Operation at sub-threshold supply voltages can significantly reduce the power dissipation of memory arrays, however it also results in lower noise margins and much higher susceptibility to radiation effects, such as soft errors or single event upsets (SEU).",

author = "Robert Giterman and Adam Teman and Lior Atias and Alexander Fish",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 ; Conference date: 05-10-2015 Through 08-10-2015",

year = "2015",

month = nov,

day = "20",

doi = "10.1109/S3S.2015.7333525",

language = "אנגלית",

series = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015",

address = "ארצות הברית",

}

Giterman, R, Teman, A, Atias, L & Fish, A 2015, A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications. in 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015., 7333525, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Institute of Electrical and Electronics Engineers Inc., IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015, Rohnert Park, United States, 5/10/15. https://doi.org/10.1109/S3S.2015.7333525

A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications. / Giterman, Robert; Teman, Adam; Atias, Lior et al.
2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7333525 (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications

AU - Giterman, Robert

AU - Teman, Adam

AU - Atias, Lior

AU - Fish, Alexander

PY - 2015/11/20

Y1 - 2015/11/20

N2 - Embedded memories often constitute over 50% of the total silicon area and are the main consumer of static power in ultra-low power (ULP) applications. Operation at sub-threshold supply voltages can significantly reduce the power dissipation of memory arrays, however it also results in lower noise margins and much higher susceptibility to radiation effects, such as soft errors or single event upsets (SEU).

AB - Embedded memories often constitute over 50% of the total silicon area and are the main consumer of static power in ultra-low power (ULP) applications. Operation at sub-threshold supply voltages can significantly reduce the power dissipation of memory arrays, however it also results in lower noise margins and much higher susceptibility to radiation effects, such as soft errors or single event upsets (SEU).

UR - https://www.scopus.com/pages/publications/84961770596

U2 - 10.1109/S3S.2015.7333525

DO - 10.1109/S3S.2015.7333525

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:84961770596

T3 - 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

BT - 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

Y2 - 5 October 2015 through 8 October 2015

ER -

Giterman R, Teman A, Atias L, Fish A. A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications. In 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7333525. (2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015). doi: 10.1109/S3S.2015.7333525

A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications

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