Abstract
Memory protocol commands and firmware features for storage solutions may function correctly by themselves, but due to implicit cross-feature dependencies they may exhibit incorrect behavior when exercised in combination with other features or commands. How can we effciently use a set of standalone per-feature tests to test the cross-features dependencies? We define an algorithm that is based on greedy and randomized heuristics that can produce an optimized plan for cross-feature testing within a polynomial number of steps. The algorithm is designed to meet cross-feature coverage requirements and was used to find problems in memory chip firmware with good results. We were consistently able to produce a cross-feature test plan in no more than 5 hours given a set of more than 1400 per-feature test variants. We have successfully discovered bugs caused by incorrectly handled interrupts and errors in managing a shared resource, that would have been missed by the per-feature tests method.
Original language | English |
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Title of host publication | 2017 IEEE International High Level Design Validation and Test Workshop, HLDVT 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1-8 |
Number of pages | 8 |
ISBN (Electronic) | 9781509039975 |
DOIs | |
State | Published - 5 Dec 2017 |
Externally published | Yes |
Event | 19th IEEE International High Level Design Validation and Test Workshop, HLDVT 2017 - Santa Cruz, United States Duration: 5 Oct 2017 → 6 Oct 2017 |
Publication series
Name | 2017 IEEE International High Level Design Validation and Test Workshop, HLDVT 2017 |
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Volume | 2017-January |
Conference
Conference | 19th IEEE International High Level Design Validation and Test Workshop, HLDVT 2017 |
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Country/Territory | United States |
City | Santa Cruz |
Period | 5/10/17 → 6/10/17 |
Bibliographical note
Publisher Copyright:© 2017 IEEE.
Keywords
- Combinatorial interaction testing
- Concurrent testing
- Constraints
- Greedy testing
- Random testing