A radiation-hardened design flow for advanced SOC

Tuvia Liran, Ran Ginosar, Dov Alon

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


The technology and design flow used for developing two advanced Systems On Chip is described. The chips are JPIC, an image compression ASIC using JPEG2000 standard, and GR712RC, a dual core LEON3FT processor. Both chips employ the Rad-Hard-By-Design RadSafe™ technology, and are implemented on a standard 0.18μm CMOS technology. Each chip size is 12×12mm, integrating more than 40 million transistors. RadSafe™ technology provides very high immunity to all radiation effects. The library was designed for high immunity to radiation and high reliability. It includes standard cells, SRAMs, all-digital DLL and I/O cells. It was proven on several test chips, demonstrating TID immunity in excess of 300Krad, proven SEL above 80MeV and SEU at 20μ2 cross section (10-12 errors/bit/day). Logic design includes EDAC, memory BIST, and techniques to minimize soft errors. Logic synthesis was performed with large timing margins and scan insertion. Physical synthesis includes a robust power grid, careful placement of I/O cells, immunity to process sensitivities, robustness to thermomechanical stress and packaging reliability. A custom 240 pins CQFP ceramic package for GR712RC was optimized for mechanical stress, hermeticity, improved supply connection for reduced impedance, and robustness to handling. A custom 208 pins PQFP plastic package was designed for JPIC.

Original languageEnglish
Title of host publicationProceedings of the DASIA 2010 Conference - DAta Systems in Aerospace
StatePublished - 2010
Externally publishedYes
EventConference on DAta Systems in Aerospace, DASIA 2010 - Budapest, Hungary
Duration: 1 Jun 20104 Jun 2010

Publication series

NameEuropean Space Agency, (Special Publication) ESA SP
Volume682 SP
ISSN (Print)0379-6566


ConferenceConference on DAta Systems in Aerospace, DASIA 2010


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