A novel low power bitcell design featuring inherent SEU prevention and self correction capabilities

Oron Chertkow, Ariel Pescovsky, Lior Atias, Alexander Fish

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed “SEU Hardening Incorporating Extreme Low Power Bitcell Design” (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel “cut-off” network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700mV supply voltage in a 65 nm process. To validate the bitcell’s robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined.

Original languageEnglish
Pages (from-to)130-150
Number of pages21
JournalJournal of Low Power Electronics and Applications
Issue number2
StatePublished - 2015

Bibliographical note

Publisher Copyright:
© 2015 by the authors; licensee MDPI, Basel, Switzerland.


  • Critical charge
  • Low power
  • Low voltage
  • SEU
  • SRAM
  • Soft errors


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