A low-complexity, low-power digital correlator for wakeup receivers is presented. With the proposed algorithm, unnecessary computational cycles are dynamically pruned from the correlation using an early threshold check. For the algorithm, we provide a rigorous mathematical analysis for the associated complexity/performance trade-offs. Furthermore, a low overhead hardware architecture with early-termination capability is developed and implemented in a 0.18μm CMOS technology. The post layout power analysis shows that the presented architecture can reduce power by up to 32% when compared to the conventional architecture with negligible degradation in detection probability and without degradation in false-alarm probability.
|Title of host publication||ISCAS 2016 - IEEE International Symposium on Circuits and Systems|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - 29 Jul 2016|
|Event||2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada|
Duration: 22 May 2016 → 25 May 2016
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Conference||2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016|
|Period||22/05/16 → 25/05/16|
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© 2016 IEEE.