A Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory

Anatoli Mordakhay; Yevgeniy Telepinsky; Lior Klein; Joseph Shor; Alexander Fish

doi:10.1109/tcsi.2017.2743045

A Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory

Anatoli Mordakhay, Yevgeniy Telepinsky, Lior Klein, Joseph Shor, Alexander Fish

Bar-Ilan University

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

A unique readout circuit topology aimed at integration with a novel type of magnetic random access memory (MRAM) is presented. The properties of the new MRAM bitcell are introduced, and the specifics of the circuit used to interface with the CMOS circuitry are described. The noise transfer function and effectiveness of the proposed topology with its practical limitations are discussed. Post-silicon measurement results verify the validity of this topology. Integration of the proposed readout circuit with the MRAM bitcells is discussed. Measurement results show an integrated input noise of 89μ Vrms, and reliable sensing of signal level of 1 mV.

Original language	English
Pages (from-to)	1224-1233
Number of pages	10
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	65
Issue number	4
DOIs	https://doi.org/10.1109/tcsi.2017.2743045
State	Published - Apr 2018

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

MRAM
Memory
non-volatile memory (NVM)
sense amplifier

Access to Document

10.1109/tcsi.2017.2743045

Cite this

@article{b34029d032c3468f983b94d1b23a6da1,

title = "A Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory",

abstract = "A unique readout circuit topology aimed at integration with a novel type of magnetic random access memory (MRAM) is presented. The properties of the new MRAM bitcell are introduced, and the specifics of the circuit used to interface with the CMOS circuitry are described. The noise transfer function and effectiveness of the proposed topology with its practical limitations are discussed. Post-silicon measurement results verify the validity of this topology. Integration of the proposed readout circuit with the MRAM bitcells is discussed. Measurement results show an integrated input noise of 89μ Vrms, and reliable sensing of signal level of 1 mV.",

keywords = "MRAM, Memory, non-volatile memory (NVM), sense amplifier",

author = "Anatoli Mordakhay and Yevgeniy Telepinsky and Lior Klein and Joseph Shor and Alexander Fish",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2018",

month = apr,

doi = "10.1109/tcsi.2017.2743045",

language = "אנגלית",

volume = "65",

pages = "1224--1233",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1549-8328",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - A Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory

AU - Mordakhay, Anatoli

AU - Telepinsky, Yevgeniy

AU - Klein, Lior

AU - Shor, Joseph

AU - Fish, Alexander

PY - 2018/4

Y1 - 2018/4

N2 - A unique readout circuit topology aimed at integration with a novel type of magnetic random access memory (MRAM) is presented. The properties of the new MRAM bitcell are introduced, and the specifics of the circuit used to interface with the CMOS circuitry are described. The noise transfer function and effectiveness of the proposed topology with its practical limitations are discussed. Post-silicon measurement results verify the validity of this topology. Integration of the proposed readout circuit with the MRAM bitcells is discussed. Measurement results show an integrated input noise of 89μ Vrms, and reliable sensing of signal level of 1 mV.

AB - A unique readout circuit topology aimed at integration with a novel type of magnetic random access memory (MRAM) is presented. The properties of the new MRAM bitcell are introduced, and the specifics of the circuit used to interface with the CMOS circuitry are described. The noise transfer function and effectiveness of the proposed topology with its practical limitations are discussed. Post-silicon measurement results verify the validity of this topology. Integration of the proposed readout circuit with the MRAM bitcells is discussed. Measurement results show an integrated input noise of 89μ Vrms, and reliable sensing of signal level of 1 mV.

KW - MRAM

KW - Memory

KW - non-volatile memory (NVM)

KW - sense amplifier

UR - http://www.scopus.com/inward/record.url?scp=85029147001&partnerID=8YFLogxK

U2 - 10.1109/tcsi.2017.2743045

DO - 10.1109/tcsi.2017.2743045

M3 - ???researchoutput.researchoutputtypes.contributiontojournal.article???

SN - 1549-8328

VL - 65

SP - 1224

EP - 1233

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 4

ER -

A Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory

Abstract

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this