A low energy dual-mode adder

Shmuel Wimer, Amir Albeck, Israel Koren

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

VLSI designs are typically data-independent and as such, they must produce the correct result even for the worst-case inputs. Adders in particular assume that addition must be completed within prescribed number of clock cycles, independently of the operands. While the longest carry propagation of an n-bit adder is n bits, its expected length is only O(log2 n) bits. We present a novel dual-mode adder architecture that reduces the average energy consumption in up to 50%. In normal mode the adder targets the O(log2 n)-bit average worst-case carry propagation chains, while in extended mode it accommodates the less frequent O(n)-bit chain. We prove that minimum energy is achieved when the adder is designed for O(log2 n) carry propagation, and present a circuit implementation. Dual-mode adders enable voltage scaling of the entire system, potentially supporting further overall energy reduction. The energy-time tradeoff obtained when incorporating such adders in ordinary microprocessor's pipeline and other architectures is discussed.

Original languageEnglish
Pages (from-to)1524-1537
Number of pages14
JournalComputers and Electrical Engineering
Volume40
Issue number5
DOIs
StatePublished - Jul 2014

Bibliographical note

Funding Information:
This research was partially funded by the Israel Science Foundation (ISF) under Grant Number 1678/13 and by the MAGNET Program of Israel Ministry of Industry (Alpha consortium). The authors wish to thank Mickey Geftler and Ophir Turbovich of CSR (formerly Zoran) for helpful discussions.

Fingerprint

Dive into the research topics of 'A low energy dual-mode adder'. Together they form a unique fingerprint.

Cite this