Abstract
An SRAM PUF with an internal error reduction mechanism is presented. A capacitive preselection test identifies potentially unstable cells with insufficient mismatch. The test can be accomplished in one VDD/temperature corner. An implementation in TSMC 65nm technology disqualified all the unstable cells (19.7%) in 14 800-bit arrays. The test has no impact on the randomness of the PUF and negligible impact on area. A highly competitive pre-ECC BER of 7.4E-10 and an energy consumption of 16fJ/bit were achieved.
| Original language | English |
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| Title of host publication | 2019 IEEE Custom Integrated Circuits Conference, CICC 2019 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781538693957 |
| DOIs | |
| State | Published - Apr 2019 |
| Event | 40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, United States Duration: 14 Apr 2019 → 17 Apr 2019 |
Publication series
| Name | Proceedings of the Custom Integrated Circuits Conference |
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| Volume | 2019-April |
| ISSN (Print) | 0886-5930 |
Conference
| Conference | 40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 |
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| Country/Territory | United States |
| City | Austin |
| Period | 14/04/19 → 17/04/19 |
Bibliographical note
Publisher Copyright:© 2019 IEEE.
Funding
ACKNOWLEDGMENT This research was sponsored by the Israel Authority through the Kamin program. This research was sponsored by the Israel Innovation Authority through the Kamin program.
| Funders | Funder number |
|---|---|
| Israel Innovation Authority | |
| Israel National Road Safety Authority |
Keywords
- Hardware security
- PUFs
- preselection
- style