A Highly Reliable SRAM PUF with a Capacitive Preselection Mechanism and pre-ECC BER of 7.4E-10

Avi Miller, Yizhak Shifman, Yoav Weizman, Osnat Keren, Joseph Shor

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

An SRAM PUF with an internal error reduction mechanism is presented. A capacitive preselection test identifies potentially unstable cells with insufficient mismatch. The test can be accomplished in one VDD/temperature corner. An implementation in TSMC 65nm technology disqualified all the unstable cells (19.7%) in 14 800-bit arrays. The test has no impact on the randomness of the PUF and negligible impact on area. A highly competitive pre-ECC BER of 7.4E-10 and an energy consumption of 16fJ/bit were achieved.

Original languageEnglish
Title of host publication2019 IEEE Custom Integrated Circuits Conference, CICC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538693957
DOIs
StatePublished - Apr 2019
Event40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019 - Austin, United States
Duration: 14 Apr 201917 Apr 2019

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2019-April
ISSN (Print)0886-5930

Conference

Conference40th Annual IEEE Custom Integrated Circuits Conference, CICC 2019
Country/TerritoryUnited States
CityAustin
Period14/04/1917/04/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Keywords

  • Hardware security
  • PUFs
  • preselection
  • style

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